HV9808

HV9708 SUTEX | Alldatasheet

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Features

❏ Processed with HVCMOS® technology ❏ Output voltages up to 80V ❏ Low power level shifting ❏ Shift register speed 8MHz ❏ Latched data outputs ❏ Forward and reverse shifting options ❏ Diode to VPP allows efficient power recovery ❏ 5V CMOS compatible inputs HV9708 HV9808 General Description The HV97 and HV98 are low-voltage serial to high-voltage paral- lel converters with push-pull outputs. These devices have been designed for use as drivers for AC-electroluminescent displays. They can also be used in any application requiring multiple output high-voltage current sourcing and sinking capabilities such as driving plasma panels, vacuum fluorescent displays, or large matrix LCD displays. The inputs are fully CMOS compatible. These devices consist of a 32-bit shift register, 32 latches, and control logic to perform the polarity select and blanking of the outputs. HV OUT1 is connected to the first stage of the shift register through the polarity and blanking logic. Data is shifted through the shift register on the logic low to high transition of the clock. The HV97 shifts data in the clockwise direction when viewed from the top of the package and the HV98 shifts in the counterclockwise direction. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (HV OUT32). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) in- puts. Transfer of data from the shift register to the latch occurs when the LE (latch enable) input is high. The data in the latch is stored when LE is low. Absolute Maximum Ratings1 Supply voltage, VDD 2 -0.5V to +7V Output voltage, VPP

2 VDD to +90V

Logic input levels2 -0.5V to VDD +0.5V Ground current3 1.5A Continuous total power dissipation4 1200mW Operating temperature range -40 °C to +85°C Storage temperature range -65 °C to +150°C Lead temperature 1.6mm (1/16 inch) 260 °C from case for 10 seconds Notes: 1. Device will survive (but operation may not be specified or guaranteed) at these extremes. 2. All voltages are referenced to GND. 3. Duty cycle is limited by the total power dissipated in the package. 4. For operation above 25 °C ambient, derate linearly to 70°C at 12mW/°C. Package Options

Recommended Operating Conditions Symbol Parameter Min Max Units Comments VDD Logic Voltage Supply 4.5 5.5 V VPP High Voltage Supply 8.0 80 V VIH Input HIGH Voltage V DD-0.5 V DD V VIL Input LOW Voltage 0 0.5 V fCLK Clock Frequency 0 8 MHz TA Operating free-air temperature -40 +85 °C Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply V DD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply V PP. Power-down sequence should be the reverse of the above. 5. The V PP should not drop below VDD or float during operations. Electrical Characteristics (VPP = 60V, VDD = 5V, TA =25°C) DC Characteristics Symbol Parameter Min Max Units Conditions IPP VPP Supply Current 100 µAH V OUT outputs HIGH to LOW IDDQ IDD Supply Current (Quiescent) 100 µA All inputs = VDD or GND IDD IDD Supply Current (Operating) 15 mA V DD = VDD max, fCLK = 8 MHz VOH (Data) Shift Register Output Voltage V DD-0.5 V I O = -100µA VOL (Data) Shift Register Output Voltage 0.5 V I O = 100µA IIH Current Leakage, any input 1 µA Input = VDD IIL Current Leakage, any input -1 µA Input = GND VOC HVOUT Output Clamp Diode Voltage -1.5 V I OC = -5mA VOH HVOUT Output when Sourcing 52 V I OH = -20mA, 0 to 70°C VOL HVOUT Output when Sinking 4 V I OL = 5mA, 0 to 70°C AC Characteristics Symbol Parameter Min Max Units Conditions fCLK Clock Frequency 8 MHz tWL or tWH Clock width, HIGH or LOW 62 ns tSU Setup time before CLK rises 25 ns tH Hold time after CLK rises 10 ns tDLH (Data) Data Output Delay after L to H CLK 110 ns C L = 15pF tDHL (Data) Data Output Delay after H to L CLK 110 ns C L = 15pF tDLE LE Delay after L to H CLK 50 ns tWLE Width of LE Pulse 50 ns tSLE LE Setup Time before L to H CLK 50 ns tON Delay from LE to HVOUT, L to H 500 ns tOFF Delay from LE to HVOUT, H to L 500 ns HV9708/HV9808

Logic Data Output High Voltage Outputs VDD Switching Waveforms Input and Output Equivalent Circuits Latch Enable HVOUT w/ S/R LOW Data Valid50% 50%Data Input Clock Data Out 50% 50% 50% tSU tH tWL tWH 50% 50% tDLH tDHL 50% tWLEtDLE tSLE 50% 50% tON 10% HVOUT w/ S/R HIGH 90% 90%10% tOFF VIH VIL VIH VIL VOH VOL VOH VOL VIH VOL VOH VOL VOH VOL

(Outputs 3 to 30 not shown) Polarity Blanking Latch Enable Data Input Clock Data Out 32-Bit Shift Register Latch Latch Latch Latch VPP Functional Block Diagram Function Table Data CLK LE BL POL Transparent latch mode Load latches Inputs Outputs Function Shift Reg HV Outputs Data Out 12 … 32 1 2 … 32 * All on X X X L L * * … *H H … H* All off X X X L H * * … *L L … L* Notes: H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition. * = dependent on previous stage’s state before the last CLK or last LE high.

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 02/06//02 ©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. Pin Configurations HV97

44 Pin J-Lead Package

4H V OUT 14 26 Latch Enable 5H V OUT 13 27 Data In 6H V OUT 12 28 Blanking 7H V OUT 11 29 NC 8H V OUT 10 30 HVout 32 9H V OUT 93 1 H V OUT 31

10 HV OUT 83 2 H V OUT 30

11 HV OUT 73 3 H V OUT 29

12 HV OUT 63 4 H V OUT 28

13 HV OUT 53 5 H V OUT 27

14 HV OUT 43 6 H V OUT 26

15 HV OUT 33 7 H V OUT 25

16 HV OUT 23 8 H V OUT 24

17 HV OUT 13 9 H V OUT 23

18 Data Out 40 HV OUT 22

19 NC 41 HV OUT 21

20 NC 42 HV OUT 20

21 Polarity 43 HV OUT 19

22 Clock 44 HV OUT 18

4H V OUT 19 26 Latch Enable 5H V OUT 20 27 Data In 6H V OUT 21 28 Blanking 7H V OUT 22 29 NC 8H V OUT 23 30 HV OUT 1 9H V OUT 24 31 HV OUT 2

10 HV OUT 25 32 HV OUT 3

11 HV OUT 26 33 HV OUT 4

12 HV OUT 27 34 HV OUT 5

13 HV OUT 28 35 HV OUT 6

14 HV OUT 29 36 HV OUT 7

15 HV OUT 30 37 HV OUT 8

16 HV OUT 31 38 HV OUT 9

17 HV OUT 32 39 HV OUT 10

18 Data Out 40 HV OUT 11

19 NC 41 HV OUT 12

20 NC 42 HV OUT 13

21 Polarity 43 HV OUT 14

22 Clock 44 HV OUT 15

39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 top view 44-pin J-Lead Package HV9708/HV9808