HV9606

HV9606 SUTEX | Alldatasheet

Document overview

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Technical content

Features

‰ Synchronous Forward, Forward, and Flyback Controller ‰ Lowest External Parts Count, Smallest Magnetics ‰ Eliminates Bootstrap Transformer Winding ‰ Supervisor Circuit Reduces Output Capacitance* up to 40% ‰ Supervisor Circuit Functions as µP Supply Monitor and POR ‰ 15V to 250V Start-Up Regulator with START/STOP Control ‰ <1mA Operating, <6µA Standby Input Current ‰ VDD Powered Operation down to 2.9V ‰ Charge Pump Gate Drive Supply ‰ Programmable Soft Start ‰ Under Voltage Lockout with Programmable Hysteresis ‰ <50% Duty Cycle Operation ‰ 15kHz to 400kHz Fixed Frequency PWM Operation ‰ Fault Tolerant Peer-to-Peer Synchronization ‰ Precision !1% Band Gap Voltage Reference ‰ Current Sense Leading Edge Blanking ‰ Small SSOP-20 Footprint *For short duration line loss, supervisor disables soft start if output within tolerance when VIN returns and thus reduces holdup requirements.

Applications

‰ Powered Ethernet and VoIP Terminals ‰ Cable Modems and Amplifiers ‰ ISDN Network Terminations, Terminals and Adapters ‰ Network Equipment ‰ Servers, PCs and Peripheral Equipment ‰ Telecommunication Systems and Terminals ‰ Distributed Board Mounted Power ‰ Battery Backup Systems ‰ Portable Power Applications ‰ Automotive and Heavy Equipment Typical Application Circuit General Description The HV9606 PWM controller allow s the design of high efficiency (>90%) power supplies for distributed board mounted power (BMP) applications. Due to its high frequency capability it can provide high currents (20A @ 3.3V) with small transformers and due to its low internal operating voltage and cu rrent is also able to achieve high efficiencies in low power applications. The HV9606 utilizes fixed frequency current mode control with duty cycle internally limited to <50%. It supports both isolated and non- isolated topologies and provides a ll the necessary functions to implement a fly back, forw ard or synchronous forw ard converter with a minimum of external parts. Due to its low VDD operation the bootstrap magnetic winding is eliminated in non-isolated topologies. An on chip charge pump generates the gate drive voltage for driving an external N-channel MOSFET and eliminates the need for clamping by offering 250V immunity to high voltage transients common in telecom and netw ork systems. It conforms to the requirements of IEEE 802.3 Pow ered Ethernet and ETR-080 ISDN specifications. The oscillator is programmable and provides fault tolerant peer-to- peer synchronization to other similar circuits or master clock. The chip draw s almost no current (<6µA @ V IN < 20V) until the programmable START/STOP threshol ds of the start-up regulator are satisfied. It can also be pow ered via the V DD pin, rather than the VIN pin, in the range of 2.9V to 5.5V. Other functions include leading edge current sense blanking, programmable SOFT START, precision !1% band gap reference and a SUPERVISOR CIRCUIT. The SUPERVISOR can provide housekeeping functions such as µP supply monitoring and reset, soft start inhibit for rapid restart on short duration input voltage interruption. It also minimi zes input and output capacitance requirements. VDD START STOP Vin REF SS SYNC RT SGND PGND STATUS SENSE FB COMP NI CA CB VX2 GATE CS HV9606 To SYNC pin of other HV9606 PWMs. +48V GND +3.3V GND To uP RESET Pin. C7 C8 C10 T1 D1 R10 10W Non-Isolated 48V to 3.3V Flyback Converter

2 4/15/2002-R.L2 HV9606 Electrical Characteristics (-40°C TA +85°C unless otherwise noted) Symbol Parameter Min Typ Max Units Conditions Pre-Regulator/Start-up VIN Regulator input voltage 15 250 V IIN Input leakage current 6 µA VIN 20V, Start = 0V, Stop = 0V IIN Input leakage current 50 µA VIN = 250V VDD(REG) Regulator output voltage 2.8 2.9 3.0 V Vin < 120V UVLOVDD VDD Under voltage lockout threshold 2.7 2.8 2.9 V VDD rising UVLOVDD VDD Under voltage lockout hysteresis 100 200 mV Supply (Test Condition: 0.1µF CA to CB and 0.1µF VX2 to PGND) VDD Operating range 2.9 5.5 V IDD Supply current 1.0 1.5 mA GATE open, fOSC = 50 kHz, VDD = 3.3V VVX2 Gate drive charge pump supply 1.8xVDD V UVLOVX2 VX2 Under voltage lockout threshold 4.5 V UVLOVX2 VX2 Under voltage lockout hysteresis 0.4 V Start/Stop Control VSTART Start threshold 6.44 7.00 7.56 V VIN rising VSTOP(MAX) Maximum voltage 13 V VSTOP Stop threshold 6.44 7.00 7.56 V VIN falling, VSTART = 0V ISTART Start input current 50 nA 6.44V VSTART 7.56V, VSTOP is open ISTOP Stop input current 50 nA 6.44 VSTOP 7.56V, VSTART to 10V via 10k MOSFET Driver Output (Test condition: VVX2 = 5V) VGATE(HIGH) Output high voltage VVX2-0.2 V IGATE = 10mA VGATE(LOW) Output low voltage 0.15 V IGATE = -10mA tR Rise time 30 50 nSec CLOAD = 250pF tF Fall time 30 50 nSec CLOAD = 250pF Oscillator fOSC Initial accuracy 10 % fOSCRANGE Oscillator Frequency Range 30 800 kHz TC Temperature coefficient 100 300 PPM/ºC fOSC = 100 kHz ∆f/f Voltage stability 1 2 % fOSC = 100 kHz, 2.9V VDD 5.5V SYNC IOSYNC Sync output current 10 20 µA IISYNC Sync input current 10 mA VSYNC < 0.1 Volt IVSYNC Sync input voltage absolute limits -0.5 VDD+0.5 V PWM FPWM PWM Oscillation Frequency 15 400 kHz FPWM = fOSC/2, Stability as fOSC above DMAX Maximum duty cycle 49.99 % fOSC = 30kHz DMAX Maximum duty cycle 49 % fOSC = 800kHz DMIN Minimum pulse width before pulse drop out 130 195 nSec VDD = 3.3V DMIN Minimum duty cycle 0 % VFB > VNI, VSS > 2V DMIN Minimum duty cycle 0 % VFB < VNI, VSS < 0.1V Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

3 4/15/2002-R.L2 HV9606 Electrical Characteristics – Continued Symbol Parameter Min Typ Max Units Test Conditions Reference VREF Reference output voltage 1.2402 V TA = 25ºC, 2.4V VDD 5.5V VREF Reference output voltage tolerance 1 % TA = 25ºC, 2.4V VDD 5.5V VREF Reference output voltage tolerance 2 % -40ºC TA 85ºC, 2.4V VDD 5.5V VREF Load regulation 2 5 mV 0 < IREF < 0.1 mA VREF Line regulation 2 5 mV 2.4V VDD 5.5V IREF(SHORT) Short circuit current 3 mA VREF = GND Current Sensing (Test conditions: VDD = 3.3V) VCS Usable control current sense range 0 0.59 V VCS Current limit threshold 0.48VREF 0.50VREF 0.52VREF V VCS Leading edge current sense blanking time 85 nSec tDELAY Current limit delay to output 70 120 nSec VCS = 0 to 1V step after blanking time Error Amplifier (Test conditions: 2.9V VDD 5.5V) IFB or INI Input bias current 25 200 nA VFB = 1.5V, VNI = 1.5V VFB - VNI Input offset voltage ±3 mV VFB = VCOMP, VNI = 1.5V VCM Common mode input range 0 VDD–0.1 V AVOL Open loop voltage gain 65 dB BW Unity gain bandwidth 1 MHz ISOURCE Output current sourcing 1 2 mA VFB < VNI ISINK Output current sinking -100 µA VFB > VNI VCOMP Output voltage range 0 VDD–0.7 V PSRR Power supply rejection 50 dB FOSC = 100 kHz Soft Start VSS(LOW) Soft start low output 0.1 V VDD = 2.9V, VSENSE = 0V, VCS = 2.9V VSS(HI) Soft start high output 2.5 VDD V VDD = 2.9V, VSENSE = 2.9V, VCS = 2.9V ISS(HI) Soft start output current 10 20 µA VDD = 2.9V, VSENSE = 2.9V, VCS = 2.9V tF Soft start output fall time 10 µSec CSS = 0.1µF Status Output (Test conditions: 2.7V VDD 5.5V) ISINK Output current sinking 5 10 mA VSTATUS = 0.5V ISOURCE Output current sourcing 10 20 µA VSTATUS = (VDD - 0.5V) VSTATUS(HIGH) High output voltage VDD-0.1 VDD V No load VSTATUS(LOW) Low output voltage 0.1 0.2 V Sinking 2mA VSENSE(THLH) Sense input threshold for rising input 0.85VREF + 0.050 0.85VREF + 0.075 0.85VREF + 0.100 V VSTATUS = LOW to HIGH transition VSENSE(THHL) Sense input threshold for falling input 0.85VREF - 0.050 0.85VREF - 0.075 0.85VREF - 0.100 V VSTATUS = HIGH to LOW transition VSENSE(HYST) Sense input hysteresis 100 150 200 mV Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

4 4/15/2002-R.L2 HV9606 Absolute Maximum Ratings* V Input Voltage -0.3V to +250V Supply Voltage, VDD -0.3V to +6V Gate Drive Supply Voltage, VX2 -0.3 to +15V Operating Ambient Temperature Range -40°C to +85°C Storage Temperature Range -65°C to +150°C Power Dissipation @ 25°C, SSOP 750mW Power Dissipation @ 25°C, Plastic DIP 750mW *All voltages referenced to SGND and PGND pins.

Ordering Information

VDD – This is the supply pin for the PWM Logic and Analog circuits. When the input voltage to the VIN pin exceeds the start voltage the input regulator seeks to regulate the voltage on the capacitor connected to this pin to a nomi nal 2.9V. After the PWM has started, the bootstrap supply will regulate this voltage to a nominal 3.3V or 5V. With V IN connected to PGND the circuit can be powered via this pin in the voltage range of 2.9V to 5.5V w ith a nominal 2.8V UVLO. START – The resistive divider from V IN sets the start-up regulator start voltage. STOP – The resistive divider from V IN sets the start-up regulator stop voltage. A low pow er sleep mode function may be implemented by pulling this pin to SGND. VIN – This is the startup linear regul ator input. It can accept DC input voltages in the range of 15V to 250V. With START and STOP programmed to more than 20V, the leakage current on this pin is less than 6µA at VIN = 20V. VREF – This pin provides a !1% tolerance reference voltage. SS – A capacitor connected to this pin determines the soft start time. Soft start may be initiated by a low VX2 voltage or an over current condition w hen supervisor ci rcuit STATUS output is low. During short duration input interruptions w hen the output voltage does not decay below programmed limits, the supervisor circuit inhibits soft start to permit rapid recovery of the system. SYNC – This I/O pin may be connected to the SY NC pin of other HV9606 circuits and will cause the oscillators to lock to the highest frequency oscillator. Synchronization to a master clock is possible by means of an open collector or open drain logic gate or optocoupler, provided the low duty cycle does not exceed 50%. If synchronization is utilized then a pull up resistor to VDD is required to overcome the effects of pa rasitic capacitance on the circuit board. The value of the resistor required w ill depend on the operating frequency and master clock duty cycle. RT – The resistor connected from this pin to SGND sets the frequency of the internal oscillator by setting the charging current for the internal timing capacitor. The PWM output frequency is one half the oscillator frequency. SGND – Common connection for all Logic and Analog circuits. PGND – Common connection for Gate Driver circuit. CS – This is the current sense input. Under normal operation the over current limit is triggered when the voltage on this pin exceeds 0.5VREF, however, current sensing is blanked during the first 85ns on time of the MOSFET to prevent false triggering during the turn on sw itching transition. The loop control operating peak current sense may be set to any level below 0.5VREF. GATE – This push-pull CMOS output is designed to drive the gate of an N-Channel power MOSFET. VX2 – This is the supply pin for the Gate Driver circuit and is generated by the Charge Pump V DD voltage doubler circuit. It should be bypassed to PGND with a capacitor, typically 0.1µF. CA and CB – The charge pump circuit uses a capacitor (ty pically 0.01µF) connected between these pins to generate the VX2 voltage. NI – High impedance non-inverting input of the error amplifier. COMP – The output of the error amplifier. FB – High impedance inverting input of the error amplifier. SENSE – This is the input pin to t he supervisory circuit. On a rising input voltage the circuit changes state at a nominal 0.85VREF + 0.075V. When the input voltage is decaying the circuit changes state a nominal 0.85VREF – 0.075V. STATUS – This is the output of the supervisory circuit. When the sense-input voltage is high, th is output is pulled up to V DD by a 10µA current source and the Soft Star t function is disabled. When the sense-input is low, this output is pulled low and it may be used to directly control the reset of a microprocessor or it may be used to drive an optocoupler or LED indicator. Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

5 4/15/2002-R.L2 HV9606 Functional Block Diagram C Vdd UVLO C Start-Up Regulator VddVin STOP START Regulator Enable RT SYNC Bandgap Reference Generator Programable Start/Stop Circuit FB A COMP C S R R Q CS Supervisor Circuit Soft Start Circuit Oscillator SSSTATUS SENSE GATE Soft Start Enable VREF PGND CLK DQ Q CLR ___ 85 nS Delay Voltage Doubler VX2 CA CB SGND C VX2 UVLO Vdd NI R R Current Limit Oscillator Enable Functional Description The HV9606 is composed of several functional blocks. The operation of each of these blocks is described in the following sections. Programmable Start/Stop Control Circuit (Programmable Under Voltage Lockout and Hysteresis) The START/STOP control circui t is a novel version of a programmable under voltage lockout w ith programmable hysteresis circuit. It is novel, because it requires zero power (other than the current in the resistor divider) and keeps the startup regulator shut dow n until the START threshold voltage is exceeded, allow ing the HV9606 to achieve its low input leakage current of <6µA. One can think of the circuit as a transparent latch, such that its output is high when the START pin is above its threshold voltage and is latched w hen the STOP pin is at a voltage greater than the START pin voltage. It is unlatched w hen the STOP pin voltage falls below its threshold voltage and the START pin is below its threshold voltage. These operating conditions are me t by using a voltage divider consisting of three resistors (see typical application circuit). The voltage drop on the resistor connected to ground controls the START voltage and the additional voltage drop on the middle resistor sets the hysteresis and controls the STOP voltage. Setting the value of the middle resistor to zero results in zero hysteresis. Provided the START and STOP pin input currents are negligible in comparison to the chosen resistor divider current, the resistor values may be calculated using the following equations: R3 = (VSTART / VIN-Start) x (VIN-Stop / IResistor) R2 = [(VSTOP / VIN-Stop) x (VIN-Stop / IResistor)] – R3 R1 = (VIN-Operating / IResistor) - R2 - R3 Where: VSTART is the START pin threshold voltage (nominal 7V) VSTOP is the STOP pin threshold voltage (nominal 7V) VIN-Start is the input voltage at which starting is desired VIN-Stop is the input voltage at which shutdown is desired IResistor is the resistor divider current (>1µA) Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

6 4/15/2002-R.L2 HV9606 Functional Description – Continued Start-Up Regulator The start-up regulator guarantees a maximum VIN pin leakage current of 6 µA at 20V at the V IN pin w hile it is inhibited by the START/STOP circuit. When the effective input voltage exceeds the programmed START voltage, the regulator is turned on and seeks to provide a nominal 2.9V at the V DD pin, which is the supply voltage for all internal circuitry w ithin the HV9606 except the start/stop circuit. This regulator is capable of input voltages up to

250 Volts, which is the typical maximum arrester voltage limit used

to provide protection on telephone w ires. Due to the high voltage rating of the regulator the HV 9606 can be used for applications operating from rectified AC mains up to 140Vrms. The regulator can supply a minimum of 5mA, w hich is sufficient to pow er the internal circuitry and provide gat e drive pow er for the external MOSFET until the bootstrap circuit from the output of the PWM drives the voltage on the VDD pin higher than the regulator set point. This forces the regulator to turn off and reduce the input current at the Vin pin to leakage levels. The VDD pin is ty pically bypassed with a capacitor of at least 1 µF, which provides the peak currents required by the voltage doubler and in turn the gate driver for the external MOSFET. For low pow er applications the circuit may be operated without bootstrapping. Care should be taken to assure that the pow er dissipation in the regulator does not become excessive, as it might be if the input voltage is high and the gate drive energy required is high (operating at high frequency). Low voltage operation of the HV9606 is also possible by powering VDD from supply voltages of 2.9V to 5.5V. In these applications the Vin, START and STOP pins s hould be connected to SGND pin. When pow ering only via V DD, the START/STOP control is not available and the startup regulator circuit is not used. VDD Under Voltage Lockout To guarantee correct operation, internal circuitry is held reset by an under voltage lockout (VDD UVLO) until the regulator output voltage is at least 100mV below the startup regulator set point. To guarantee stable starting the VDD UVLO has a hy steresis of 100mV. Oscillator The oscillator circuit operates at twice the PWM output frequency. The frequency can be programmed in the range of 30kHz to 800kHz by means of a single resistor connected from the RT pin to SGND. For a given frequency the value of the resistor can be calculated using the following equation: RT = [(1 / fOSC) –1x10 ] / 42.6x10 -12 Synchronization The SYNC pin is an input/output (I/O) port to a unique fault tolerant peer-to-peer and/or to master clock sy nchronization circuit. For synchronization the SYNC pins of multiple HV9606 based converters can be connected t ogether and may also be connected to the open drain/collector output of an external master clock. When connected in this manner the oscillators will lock to the device with the highest operating frequency . The LOW duty cycle of an external master clock should not exceed 50%. When synchronized in this manner, a permanent logic HIGH or LOW condition on the SY NC pin w ill result in a loss of synchronization, but the HV9606 based converters w ill continue to operate at their individually set operating frequency. For this reason the SY NC pin is consider ed fault toler ant, sinc e loss of sy nchronization w ill not result in total system failure. Depending on the cumulative parasitic capacitance on the SY NC pin when connected in the above manner a pull up resistor may be required from the SYNC pin to the V DD pin on each HV9606 based DC/DC converter circuit. The va lue of the resistor w ill depend on the cumulative parasitic capacitance and operating frequency. Voltage Doubler The HV9606 can operate on internal voltages ranging from 2.9V to 5.5V. It may be difficult to find power MOSFETs capable of operating with such low gate drive voltages. For this reason the HV9606 incorporates a voltage doubler circuit that generates a voltage on the VX2 pin that is approximately tw o times the VDD voltage. This circuit uses c apacitive charge transfer methods and requires the connection of a capacitor (typically 0.01µF) between the CA and CB pins as w ell as an energy storage capacitor (typically 0.1 µF) connected from the VX2 pin to PGND pin. The voltage doubler operates at the PWM output frequency. The gate driver output on the GATE pin operates from the VX2 voltage, logic level (5Volt) gate pow er MOSFETs may be used when V DD is bootstrapped at 3.3V or standard (10V) gate MOSFETs may be used when VDD is bootstrapped at 5V. VX2 Under Voltage Lockout To guarantee that sufficient gate drive voltage is available, an under voltage lockout circuit (VX2 UVLO) monitors the VX2 voltage. If the VX2 voltage drops below 4.5V the gate driver output of the PWM circuit is inhibit ed to prevent damage to the power MOSFET. This under voltage lockout has a hy steresis of 400mV to prevent spurious operation. Band Gap Reference The operating limits of all inte rnal circuits, except the START/STOP circuit, are based on the !1% tolerance band gap reference voltage available on t he REF pin. It is capable of delivering 100µA for use by external circuitry without degrading the reference. A bypass capacitor of at least 0.1 µF should be connected from the REF pin to SGND pin. Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

7 4/15/2002-R.L2 HV9606 Functional Description – Continued Current Sense and Current Limit Current sensing is accomplished by means of a resistor connected in series w ith the source of t he external pow er MOSFET. There are tw o independent comparators monitoring the voltage drop across this resistor. One provides absolute peak current limiting at 0.5VREF and the other provides peak current feedback to the PWM control loop. Gate charge, capacitive loading and reverse recovery of output rectifier reflected to the drain of the pow er MOSFET results in high current spike at the positive leading edge of gate drive w hen the MOSFET is turning on. This can result in false tripping of the current limit comparator or incorrect operation of the control loop. To prevent this condition an 85nSec leading edge current sense blanking circuit is incorporated in the HV9606. This blanking period is sufficient in most applications to achieve stable operation. However, additional filtering of the MOSFET turn on current spike may be added by connecting a resistor in series with the (CS) current sense pin and a capacitor from the current sense pin to SGND pin. Error Amplifier The error amplifier has a minimum gain bandwidth of 1MHz. The inverting and non-inverting inputs are available respectively at FB and NI pins and the amplifier output is available at the COMP pin. Maximum application flex ibility is provided to the designer by having all terminals of the error am plifier available. The design of the error amplifier prevents its output from saturating to the high rail (VDD) thus providing very fast slew recovery capability. Soft Start Control Circuit The soft start circuit provides a nominal constant current output of 10µA at the SS pin for charging a capac itor connected to this pin. The instantaneous voltage on the SS pin determines the high limit of the error amplifier, thus forcing the PWM to start at minimum output duty cy cle and slow ly increase the duty cy cle until stable closed loop operation is achieved. The value of the capacitor should be selected to achieve th is stable closed loop operation before the voltage on the SS pin exceeds 1.2V at maximum output load on the DC/DC converter. Soft start can only be initiated if the STATUS output of the SUPERVISOR circuit is low. The SS pin is pulled low, discharging the capacitor and engaging soft restart w henever the VX2 UVLO detects a low gate drive voltage. PWM Circuit The current mode PWM circuit oper ates at one half the oscillator frequency with a duty cy cle guaranteed not to exceed 50%. Its minimum pulse width (typically 130nSec) provides a wide dynamic control range especially when operating at low frequencies. For the dy namic control range requi red by a given application the maximum operating frequency c an be determined using the following equations. tON = ( VIN(MAX) / VIN(MIN) ) x ( POUT(MAX) / POUT(MIN)) x DMIN fOSC = 2 fPWM < 1 / tON Where tON is the maximum gate drive output on time, V IN(MAX) and VIN(MIN) are the maximum and minimum input voltage, POUT(MAX) and POUT(MIN) are the maximum and minimum output pow er, DMIN is the worst case minimum gate drive output duty cycle (195nSec), f PWM is the maximum gate drive sw itching frequency and f OSC is the maximum oscillator frequency. Supervisor Circuit The designer may use this volt age monitor circuit for various applications. The supervisor circuit controls the function of the soft start circuit, which will be enabled w hen the STATUS output pin is in a low state. The STATUS output pin is low when the voltage on the SENSE pin is less than 0.85VREF – 100mV. The supervisory circuit can be us ed to monitor the output voltage of the DC/DC converter. When used in this manner the STATUS output pin may be used as a supply monitor and power on reset (POR) for a micro controller w henever the supply voltage decays to a programmed voltage level. Using it in this manner in a non- isolated topology, where the output voltage is used for bootstrapping VDD, it w ill inhibit soft start as long as the output is within programmed limits, thereby providing a rapid restart after a short duration input voltage dropout. This allow s the minimization of both input and output capacitors for a given sy stem hold up time requirement. In an Isolated topology, sizing the VDD capacitor for a hold up time greater than the output hold up time requirement will similarly permit the minimization of the input and output capacitors. The supervisory circuit can also be used as a high accuracy low input voltage detection and inhibit circuit by connecting the STATUS pin to the SS pin. Since the status pin has a 10 µA internal pull up it w ill double the charging current of the soft start capacitor, thus the soft start capacitor value needs to be doubled for the same soft start time. The SENSE pin may be connected through a resistor divider to any monitored voltage source (other than the output of the HV9606 based DC/DC converter) or to a logic output. When the voltage on the SENSE pin falls below 0.85VREF – 100mV, the SS pin will be pulled low , thereby inhibiting the gate drive output and shutting down the converter. The oscillator will operate even though the GATE output is held low and the SYNC I/O pin w ill maintain sy nchronization with other system components or provide a clock signal to the system. Shut Down / Inhibit Operation The HV9606 may be shut dow n or inhibited depending on the system requirements. Pulling the STOP pin down to SG ND will shut dow n the HV9606, placing it in a zero pow er (leakage only ) mode w here even the oscillator is halted. This pull dow n may be accomplished with a discrete MOSFET, an optocoupler, or the open drain/collector output of a logic gate w ith at l east 20V breakdown rating. Using this shut down method will cause the SY NC pin to be pulled low , thus synchronization of other components connected to the SYNC line will be lost. Provided the input voltage remains above the programmed stop threshold, inhibit of the PWM can be achieved by pulling the SS pin low to SGND, thereby forcing the gate drive output to a permanent low state and guaranteeing a soft restart w hen SS pin pull down is released. The internal start up regulator will power the HV9606 thus the oscillator will operate and the SY NC I/O pin w ill maintain synchronization with other system components or provide a clock signal to the sy stem. This pull dow n could be accomplished w ith a discrete MO SFET, an optocoupler, or the open drain/collector output of a logic gate w ith at least a 5V breakdown rating. Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

8 4/15/2002-R.L2 HV9606

Application Information

Typical Semi-Isolated ISDN Circuit VDD START STOP Vin REF SS SYNC RT SGND PGND STATUS SENSE FB COMP NI CA CB VX2 GATE CS HV9606+48V GND +3.3V GND To uP RESET pin. C7 C8 C10 R10 C11 C12 +5V Isolated 40V1.5W Flyback Converter Typical Isolated ISDN Circuit VDD START STOP Vin REF SS SYNC RT SGND PGND STATUS SENSE FB COMP NI CA CB VX2 GATE CS HV9606+48V GND +3.3V COM R10 C10 +5V Isolated 40V R11 6N135 R12 R13 R14 TL431 1.5W Isolated Flyback Converter C11 Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com

9 4/15/2002-R.L2 HV9606 Typical Board Mounted Power (BMP) Supply VDD START STOP Vin REF SS SYNC RT SGND PGND STATUS SENSE FB COMP NI CA CB VX2 GATE CS HV9606+48V GND 2 x Si4884DY M2 and M3 M4 and M5 2 x Si4884DY IRF530S B320A 1N4148 1.23V (+) IN (-) GND OUT 31K Rf COMP LM3411 Optional Connection to SYNC Pin of other HV9606 DC/DC Converters or Master Clock C10 C11 R10 48V to 3.3V @ 20A Isolated Synchronous Forward Converter with Resonant Core Reset MOC207 3.3V 20A R13 R11 R12 Active Snubber Circuit Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 FAX: (408) 222-4895 www.supertex.com