HV9605

HV9605 SUTEX | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 5

Technical content

Features

49% duty cycle operation Programmable START/STOP capability 15V to 250V input range internal start-up regulator 6.0mA standby supply current for +VIN <20V 0.9mA operating supply current 5.0V VDD supply operation 30KHz to 300KHz internal oscillator 15KHz to 150KHz converter output frequency 1.0MHz low offset error amplifier 1.20V 2% band gap reference Output driver optimized for under 10W applications Low driver output impedance with VDD = 0V Fast (90nsec) over current shutdown All pins are ESD protected

Applications

Absolute Maximum Ratings* +V IN, Input Voltage -0.5V to +250V Supply Voltage, VDD -0.5V to +10V Operating Temperature Range -40 °C to +85°C Storage Temperature Range -65 °C to +150°C Power Dissipation @ 25°C, SOIC 750mW Power Dissipation @ 25°C, Plastic DIP 1000mW *All voltages referenced to GND Preliminary

14 Pin 14 Pin DiePlastic DIP Narrow Body SOIC

+VIN Feedback Max Package Options Min Max Accuracy Duty Cycle 15V 250V < – 1% 49% HV9605P HV9605NG HV9605X

Ordering Information

VOUT(HIGH) Output high voltage 4.85 4.90 V I OUT = 10mA, VDD = 5.00V VOUT(LOW) Output low voltage 0.05 0.15 V I OUT = -10mA tR Rise time 30 50 nsec C L = 250pf tF Fall time 20 50 nsec C L = 250pf Oscillator

150 KHz R T = 91KW

fOUT Output converter frequency 45 50 55 KHz R T = 390KW 31.5 35 38.5 KHz R T = 560KW 18 20 22 KHz R T = 1.0MW TC Temperature coefficient 100 300 PPM/ °Cf OUT = 50KHz Df/f Voltage stability 1 3 % f OUT = 50KHz, 4.5V< VDD <5.5V Pre-Regulator/Start-Up +VIN Regulator input voltage 15 250 V +IIN Input leakage current 6.0 mA+ V IN=20V, Start=0V, Stop=0V +IIN Input leakage current 50 mA+ V IN = 250V, VDD = 4.7V +ISTART Pre-regulator start-up current 5.0 mA +V IN = 15V, Start & Stop 10MW to + VIN VDD Regulator output voltage 4.4 4.5 4.6 V UVLO Under voltage lockout threshold 4.1 4.2 4.4 V V DD rising HYST Under voltage hysteresis 0.1 0.3 0.4 V Start/Stop Control VSTART Start threshold 6.72 7.30 7.88 V ISTART Start input current 0.05 mA+ V IN = 18V ISTOP Stop input current 0.05 mA+ V IN = 18V VCLAMP Zener clamp voltage on STOP Pin 20 V

Electrical Characteristics

Symbol Parameters Min Typ Max Unit Conditions Supply VDD Operating range 4.7 8.0 V IDD Supply current 0.9 1.3 mA OUT open, fOUT = 20KHz to 150KHz, VDD = 5V

ISINK Output current sinking 5.0 10 mA V STATUS = 2.0V ISOURCE Output current sourcing 5.0 10 15 mA VSTATUS(HIGH) High output voltage V DD -0.2 V DD V No load VSTATUS(LOW) Low output voltage 1.0 2.0 V Sinking 5mA 0.02 0.04 V Sinking 100 mA tR Rise time 1.0 5.0 msec 4.7nF From Status to GND Error Amplifier VFB Feedback voltage 1.188 1.200 1.212 V REF shorted to NI, FB shorted to Comp, TA = 25°C IFB or INI Input bias current 25 200 nA V FB = 3.0V, VNI = 2.5V VOS Input offset voltage 5.0 25 mV VCM Common mode input range 0 V DD -1 V AVOL Open loop voltage gain 65 90 dB BW Unity gain bandwidth 1.0 1.5 MHz I SOURCE Output current sourcing -2 -1 mA V FB < VNI ISINK Output current sinking 2 4 mA V FB > VNI PSRR Power supply rejection 50 72 dB 4.5V < V DD < 5.5V, f=1KHz Reference VREF Reference output voltage 1.176 1.200 1.224 V T A = 25°C VREF Load regulation 1.0 5.0 mV 0 < I REF < 0.3mA VREF Line regulation 2.0 5.0 mV 3.0V < V DD < 5.5V VREF Reference output voltage 1.159 1.200 1.241 V -40 °C < TA < 85°C Long term stability 3.0 mV T A = 125°C, 1000hrs IREF(SHORT) Short circuit current 0.5 1.0 mA V REF = SGND PWM D MAX Maximum duty cycle 49.0 49.9 % f OUT = 20KHz D MIN Minimum duty cycle 0 % Minimum pulse width before pulse drop out 80 125 nsec Current Sensing VCS Usable control current sense range V CS (limit) V VCS (LIMIT) Current limit threshold 0.6 0.7 0.8 V tDELAY Current limit delay to output 90 120 nsec V CS = 1.5V Electrical Characteristics (continued) Symbol Parameters Min Typ Max Unit Conditions

14 Pin SOIC/DIP Package

SGND - Common connection for all low level signal and digital circuits. While SGND and PGND must be electrically connected together, having separate common pins enhances the ability of the designer to prevent coupling of noise into critical circuits. PGND - This pin provides common return for the high transient current of the output driver circuits. While PGND and SGND must be electrically connected, having a separate connection prevents common noise created by the high transient currents of the output driver from being injected into critical circuits. IN - This is the start-up linear pre-regulator input which can accept DC input voltages in the range of 15V to 250V. With START and STOP set to more than 20V, the leakage current on this pin is less than 6.0mA at +V IN = 20V. START - The resistive divider from +VIN sets the start voltage. STOP - The resistive divider from +VIN sets the stop voltage. VDD - This is the supply pin for the PWM circuits. When the input voltage to the +VIN pin exceeds the start voltage the input regulator seeks to regulate the voltage on the capacitor con- nected to this pin to a nominal 4.5V. OUT - This high current push-pull CMOS output is intended to drive the gate of a power MOSFET. In order to protect the power MOSFET in high electrical noise environment, this output appears as low impedance to PGND when V DD is at zero volts. CS - This is the current sense input to the PWM compara- tors. Under normal operation the over current limit is triggered when the voltage on this pin is at 0.70V and the loop control operating peak current may be set to any level below this, typically in the range of 0.2 to 0.5V. COMP - The low impedance output of the error amplifier. FB - The high impedance inverting input of the error amplifier. NI - The high impedance non-inverting input of the error amplifier. REF - This pin provides a 2% accuracy 1.20V low output impedance buffered reference which is current limited to 0.5mAmps and should be bypassed, REF to SGND, with a 0.1mF ceramic capacitor. RT - The resistor connected from this pin to SGND sets the frequency of the internal oscillator by setting the charging current for the internal timing capacitor. The oscillator frequency is twice the PWM output frequency. STATUS - This output is held low until the +V IN voltage reaches the programmed START voltage. It remains low until the boot- strap supply to V DD forces the voltage above the internal regulator set point. It is further held low while the control amplifier output on the COMP pin is forced to its high limit by a low output from the converter. Once all these conditions are satisfied, this output will rise to V DD with a time constant set by the external capacitor indicating that normal operation has been reached. This output may be used to control the reset of a microprocessor. Pin Configuration

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 744-0100 • FAX: (408) 745-4895 www.supertex.com 11/30/98 Functional Block Diagram RT CLK CLR Q A C S OUT CS PGND SGND Q R DQ REF NI FB COMP Bandgap Reference Generator V DD VDD VDD+V IN STOP START Clock Oscillator MOSFET Driver PWM Good Bootstrap Good VREF STATUS UVLO C Start-Up RegulatorEnable C VSTART H=SWITCH CLOSED L= SWITCH OPEN Typical Application Circuit VDD STATUS OUT CS PGND SGND COMPFBNIREFRT START STOP 48V INPUT +VIN HV9605 + ++ ++ 40V ISOLATED OUTPUT RESET +5.0V REFERENCED TO INPUT (-) TERMINAL TN2124K1 or TN2524N8