HV9123PJ

HV9120 SUTEX | Alldatasheet

Document overview

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Technical content

Features

❏ 10 to 450V input acceptance range ❏ <1.3mA supply current ❏ >1.0MHz clock ❏ >20:1 dynamic range @ 500KHz ❏ Low internal noise Feedback Max Accuracy Duty CycleMin Max +VIN Package Options

16 Pin 16 Pin 20 Pin DIEPlastic DIP SOIC Plastic PLCC

Voltages are referenced to -VIN +VIN Input Voltage 450V VDD Device Supply Voltage 15.5V Logic Input Voltages -0.3 to V DD + 0.3V Linear Input Voltages -0.3 to V DD + 0.3V IIN Preregulator Input Current (continuous) 2.5mA Tj Operating Junction Temperature 150 ° C Storage Temperature -65 °C to 150°C Power Dissipation, PDIP 1000mW Power Dissipation PLCC 1400mW Power Dissipation SOIC 900mW

Applications

❏ Off-line high frequency power supplies ❏ Universal input power supplies ❏ High density power supplies ❏ Very high efficiency power supplies ❏ Extra wide load range power supplies For detailed circuit and application information, please refer to application notes AN-H13 and AN-H21 to AN-H24. HV9120 HV9123 11/12/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liabi lity to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to c hange without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most curre nt databook or to the Legal/Disclaimer page on the Supertex website.

Electrical Characteristics

(Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ,TA = 25°C.) Symbol Parameters Min Typ Max Unit Conditions Reference VREF Output Voltage 3.92 4.00 4.08 V R L = 10MΩ 3.84 4.00 4.16 R L = 10MΩ, TA = -55°C to 125°C ZOUT Output Impedance1 15 30 45 K Ω ISHORT Short Circuit Current 125 250 µAV REF = -VIN ∆VREF Change in VREF with Temperature1 0.25 mV/ °CT A = -55°C to 125°C Oscillator fMAX Oscillator Frequency 1.0 3.0 MHz R OSC = 0Ω fOSC Initial Accuracy2 80 100 120 KHz R OSC = 330KΩ 160 200 240 R OSC = 150KΩ ∆VOSC Voltage Stability 15 % 9.5V < V DD <13.5V TCOSC Temperature Coefficient1 170 ppm/ °CT A = -55°C to 125°C PWM DMAX Maximum Duty Cycle1 HV9120 49.0 49.4 49.6 % HV9123 95 97 99 Deadtime1 HV9123 225 nsec DMIN Minimum Duty Cycle 0 % Minimum Pulse Width 80 125 nsec Before Pulse Drops Out 1 Current Limit Vlim Maximum Input Signal 1.0 1.2 1.4 V V FB = 0V td Delay to Output1 80 150 ns V SENSE = 1.5V, VCOMP ≤ 2.0V Error Amplifier VFB Feedback Voltage 3.92 4.00 4.08 V V FB Shorted to Comp IIN Input Bias Current 25 500 nA V FB = 4.0V VOS Input Offset Voltage nulled during trim AVOL Open Loop Voltage Gain1 60 80 dB GB Unity Gain Bandwidth 1 1.0 1.3 MHz ZOUT Output Impedance1 see fig. 1 Ω ISOURCE Output Source Current -1.4 -2.0 mA V FB = 3.4V ISINK Output Sink Current 0.12 0.15 mA V FB = 4.5V PSRR Power Supply Rejection 1 see fig. 2 dB Notes: 1. Guaranteed by design. Not subject to production test. 2. Stray C on OSC IN pin must be ≤5pF.

Electrical Characteristics (continued) (Unless otherwise specified, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ,TA = 25°C.) Symbol Parameters Min Typ Max Unit Conditions Pre-regulator/Startup +VIN Input Voltage 450 V I IN < 10µA; VCC > 9.4V +IIN Input Leakage Current 10 µAV DD > 9.4V VTH VDD Pre-regulator Turn-off Threshold Voltage 8.0 8.7 9.4 V I PREREG = 10µA VLOCK Undervoltage Lockout 7.0 8.1 8.9 V Supply IDD Supply Current 0.75 1.3 mA C L < 75pF IQ Quiescent Supply Current 0.55 mA Shutdown = -V IN IBIAS Nominal Bias Current 20 µA VDD Operating Range 9.0 13.5 V Shutdown Logic tSD Shutdown Delay1 50 100 ns C L = 500pF, VSENSE = -VIN tSW Shutdown Pulse Width1 50 ns tRW RESET Pulse Width1 50 ns tLW Latching Pulse Width1 25 ns Shutdown and reset low VIL Input Low Voltage 2.0 V VIH Input High Voltage 7.0 V IIH Input Current, Input Voltage High 1.0 5.0 µAV IN = VDD IIL Input Current, Input Voltage Low -25 -35 µAV IN = 0V Output VOH Output High Voltage V DD -0.25 V I OUT = 10mA VDD -0.3 I OUT = 10mA, TA = -55°C to 125°C VOL Output Low Voltage 0.2 V I OUT = -10mA

0.3 I OUT = -10mA,

TA = -55°C to 125°C ROUT Output Resistance Pull Up 15 25 Ω IOUT = ±10mA Pull Down 8.0 20 Pull Up 20 30 Ω IOUT = ±10mA, Pull Down 10 30 T A = -55°C to 125°C tR Rise Time1 30 75 ns C L = 500pF tF Fall Time1 20 75 ns C L = 500pF Note: 1. Guaranteed by design. Not subject to production test. HV9120/HV9123

HH → L Normal Operation, No Change L H Off, Not Latched L L Off, Latched L → H L Off, Latched, No Change Truth Table Shutdown Timing Waveforms Functional Block Diagram VDD 50% t d Output Sense 1.5V tSD 50% 90%90% VDD Output Shutdown VDD t LW 50% 50% tSW 50% 50% t RW Reset VDD Shutdown VDD 50% tR, tF ≤ 10ns tF ≤ 10ns tR ≤ 10ns HV9120/HV9123 REF GEN Modulator Comparator OSC R S Q Current Limit Comparator 9120 COMP Discharge OSC In OSC OutFB VREF BIAS VDD +VIN Pre-regulator/Startup 8.6V 8.1V Undervoltage Comparator S R Q VDD Shutdown Reset Sense IN Output Error Amplifier To Internal Circuits 1.2VCurrent Sources To VDD2V TQ 9123 5 (6) 6 (8) 4 (5) 12 (16) 13 (17) 1 (3) 7 (9) 16 (20) 11 (14) Pin number in parentheses are for PLCC package.

PSRR — Error Amplifier and Reference 1M10K100 100K 1K110 Output Switching Frequency vs. Oscillator Resistance 1M100 k10k 10k R OSC (Ω) f (Hz)OUT -10 100 1K 10K Error Amplifier Open Loop Gain/Phase RDISCHARGE vs. tOFF (9123 only) 100K 1M Gain (dB) Phase (°C) 180 120 -60 -120 -180 Frequency (Hz) 106 105 104 103 102 Error Amplifier Output Impedance (Z0) -10 -20 -30 -40 -50 -60 -70 -80 100k HV9123 HV9120 Bias Resistance (Ω) 107106105 Bias Current (µA) 100 VDD = 10V VDD = 12V PSSR (dB) Frequency (Hz) ZO (Ω) RDISCHARGE (Ω) 10310-1 102 tOFF (nsec) 103 104 ROSC = 1 00K ROSC = 1 0K ROSC = 1K 104100 105101 106102 100 1K 10K 100K 1M Frequency (Hz) 10M Typical Performance Curves Fig. 3 Fig. 1 Fig. 4 Fig. 2 Fig. 5 Fig. 6

The preregulator/startup circuit for the HV912x consists of a high- voltage n-channel depletion-mode DMOS transistor driven by an error amplifier to form a variable current path between the V IN terminal and the VDD terminal. Maximum current (about 20 mA) occurs when VDD = 0, with current reducing as VDD rises. This path shuts off altogether when VDD rises to somewhere between 7.8 and 9.4V, so that if VDD is held at 10 or 12V by an external source (generally the supply the chip is controlling) no current other than leakage is drawn through the high voltage transistor. This mini- mizes dissipation. An external capacitor between V DD and VSS is generally required to store energy used by the chip in the time between shutoff of the high voltage path and the V DD supply’s output rising enough to take over powering the chip. This capacitor should have a value of 100X or more the effective gate capacitance of the MOSFET being driven, i.e., Cstorage ≥ 100 x (gate charge of FET at 10V ÷ 10V) as well as very good high frequency characteristics. Stacked polyester or ceramic caps work well. Electrolytic capacitors are generally not suitable. A common resistor divider string is used to monitor VDD for both the undervoltage lockout circuit and the shutoff circuit of the high voltage FET. Setting the undervoltage sense point about 0.6V lower on the string than the FET shutoff point guarantees that the undervoltage lockout always releases before the FET shuts off. Bias Circuit An external bias resistor, connected between the bias pin and VSS is required by the HV912x to set currents in a series of current mirrors used by the analog sections of the chip. Nominal external bias current requirement is 15 to 20 µA, which can be set by a 390KΩ to 510K Ω resistor if a 10V V DD is used, or a 510k Ω to 680KΩ resistor if V DD will be 12V. A precision resistor is not required; ± 5% is fine. Clock Oscillator The clock oscillator of the HV912x consists of a ring of CMOS inverters, timing capacitors, a capacitor discharge FET, and, in the 50% maximum duty cycle versions, a frequency dividing flip- flop. A single external resistor between the OSC In and OSC Out pins is required to set oscillator frequency (see graph). For the 50% maximum duty cycle versions the Discharge pin is internally connected to V SS (ground). For the 99% duty cycle version, Discharge can either be connected to VSS directly or connected to VSS through a resistor used to set a deadtime. One difference exists between the Supertex HV912x and competi- tive 912x’s: The oscillator is shut off when a shutoff command is received. This saves about 150 µA of quiescent current, which aids in the construction of power supplies to meet CCITT speci- fication I-430, and in other situations where an absolute minimum of quiescent power dissipation is required. Reference The Reference of the HV912x consists of a stable bandgap reference followed by a buffer amplifier which scales the voltage up to approximately 4.0V. The scaling resistors of the reference buffer amplifier are trimmed during manufacture so that the output of the error amplifier when connected in a gain of –1 configuration is as close to 4.000V as possible. This nulls out any input offset of the error amplifier. As a consequence, even though the ob- served reference voltage of a specific part may not be exactly 4.0V, the feedback voltage required for proper regulation will be. A ≈50KΩ resistor is placed internally between the output of the reference buffer amplifier and the circuitry it feeds (reference output pin and non-inverting input to the error amplifier). This allows overriding the internal reference with a low-impedance voltage source ≤6.0V. Using an external reference reinstates the input offset voltage of the error amplifier, and its effect of the exact value of feedback voltage required. In general, because the reference voltage of the Supertex HV912x is not noisy, as some previous examples have been, overriding the reference should seldom be necessary. Because the reference of the 912x is a high impedance node, and usually there will be significant electrical noise near it, a bypass capacitor between the reference pin and V SS is strongly recom- mended. The reference buffer amplifier is intentionally compen- sated to be stable with a capacitive load of 0.01 to 0.1µF. Reference V1 V2 60.4K 40.2K 1.0V swept 100Hz – 2.2MHz Tektronix P6021 (1 turn secondary) 0.1µF +10V (VDD) GND (–VIN) (FB) NOTE: Set Feedback Voltage so that VCOMP = VDIVIDE ± 1mV before connecting transformer Error Amp ZOUT Reference 0.1V swept 10Hz – 1MHz 0.1µF 10.0V 4.00V 100K1% 100K1% PSRR

V REF Discharge OSC In Error Amplifier The error amplifier in the HV912x is a true low-power differential input operational amplifier intended for around-the-amplifier com- pensation. It is of mixed CMOS-bipolar construction: A PMOS input stage is used so the common-mode range includes ground and the input impedance is very high. This is followed by bipolar gain stages which provide high gain without the electrical noise of all-MOS amplifiers. The amplifier is unity-gain stable. Current Sense Comparators The HV912x uses a true dual comparator system with indepen- dent comparators for modulation and current limiting. This allows the designer greater latitude in compensation design, as there are no clamps (except ESD protection) on the compensation pin. Like the error amplifier, the comparators are of low-noise BiCMOS construction. Remote Shutdown The shutdown and reset pins of the HV912x can be used to perform either latching or non-latching shutdown of a converter as required. These pins have internal current source pull-ups so they can be driven from open-drain logic. When not used they should be left open, or connected to V DD. Output Buffer The output buffer of the HV912x is of standard CMOS construc- tion (P-channel pull-up, N-channel pull-down). Thus the body- drain diodes of the output stage can be used for spike clipping if necessary, and external Schottky diode clamping of the output is not required. Detailed Description (continued) +VIN NC NC Sense Output –VIN VDD OSC Out Pinout

16 Pin SOIC

Note: Pins 2 and 3 are removed

16 Pin Dip Package

V REF Discharge OSC In IN Sense Output –VIN VDD OSC Out 18 17 16 15 14 4 5 6 7 8 FB BIAS NC NC IN NC Discharge OSC In OSC Out V DD NC SenseOutput NC –V IN COMPReset Shutdown NC V REF 20-pin PJ Package top view

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