HV9120PJ-G

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Document overview

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Technical content

Features

► 10 to 450V input voltage range ► <1.3mA supply current ► >1.0MHz clock ► >20:1 dynamic range @ 500KHz ► 49% Maximum duty cycle version ► Low internal noise

Applications

► Off-line high frequency power supplies ► Universal input power supplies ► High density power supplies ► Very high efficiency power supplies ► Extra wide load range power supplies General Description The Supertex HV9120 is a Switch Mode Power Supply (SMPS) controller subsystem that can start and run directly from almost any DC input, from a 12V battery to a rectified and filtered 240V AC line. It contains all the elements required to build a single-switch converter except for the switch, magnetic assembly, output rectifier(s) and filter(s). High-Voltage, Current-Mode PWM Controller OSC R S Q COMP FB VREF BIAS VDD +VIN Pre-regulator/Startup 8.6V 8.1V S R Q VDD SHUTDOWN RESET SENSE OUTPUT 1.2V To VDD 2V T Q 5 (6) 6 (8) 4 (5) 12 (16) 13 (17) 1 (3) 7 (9) 16 (20) 11 (14) REF GEN Modulator Comparator Current Limit Comparator OSC IN OSC OUT Undervoltage Comparator Error Amplifier To Internal Circuits Current Sources -VIN A unique input circuit allows the HV9120 to self-start directly from a high voltage input, and subsequently take the power to operate from one of the outputs of the converter it is controlling, allowing very efficient operation while maintaining input-to-output galvanic isolation limited in voltage only by the insulation system of the associated magnetic assembly. A ±2% internal bandgap reference, internal operational amplifier, very high speed comparator, and output buffer allow production of rugged, high performance, high efficiency power supplies of 50W or more, which can still be over 80% efficient at outputs of 1.0W or less. The wide dynamic range of the controller system allows designs with extremely wide line and load variations with much less difficulty and much higher efficiency than usual. The exceptionally wide input voltage range also allows better usage of energy stored in input dropout capacitors than with other PWM ICs. Remote on/off controls allow either latching or nonlatching remote shutdown. During shutdown, the power required is under 6.0mW. For detailed circuit and application information, please refer to application notes AN-H13, AN-H21 to AN-H24. Functional Block Diagram Note: Pin numbers in parentheses are for PLCC package.

Supertex inc. www.supertex.com Doc.# DSFP-HV9120 B060412 Pin Configurations Product Marking 16-Lead SOIC (NG) Absolute Maximum Ratings Parameter Value Input voltage, +VIN 450V Device supply voltage, VDD 15.5V Logic input voltage -0.3V to VDD +0.3V Linear input voltage -0.3V to VDD +0.3V Pre regulator input current (continuous), IIN 2.5mA Operating junction temperature, TJ 150OC Storage temperature -65 to +150OC Power dissipation: 16-Lead SOIC 900mW 16-Lead PDIP 1000mW 20-Lead PLCC 1400mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltages are referenced to -V IN. 1 16 1 16 2012 16-Lead PDIP (P) 20-Lead PLCC (PJ) 16-Lead SOIC (NG) 16-Lead PDIP (P) 20-Lead PLCC (PJ) Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking HV9120NG YWW LLLLLLLL CCCCCCCCC AAA Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV9120P LLLLLLLLLL CCCCCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number A = Assembler ID C = Country of Origin* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW AAA HV9120PJ LLLLLLLLLL CCCCCCCCCCC Package may or may not include the following marks: Si or Package may or may not include the following marks: Si or Package may or may not include the following marks: Si or -G Indicates package is RoHS compliant (‘Green’) * Obsolescence notice issued for the product in the 20-Lead PLCC package. Part Number Package Options Packing HV9120NG-G 16-Lead SOIC 45/Tube HV9120NG-G M934 16-Lead SOIC 2500/Reel HV9120P-G 16-Lead PDIP 24/Tube HV9120PJ-G 20-Lead PLCC* 48/Tube HV9120PJ-G M910 20-Lead PLCC* 1000/Reel Typical Thermal Resistance Package θja 16-Lead SOIC 83OC/W 16-Lead PDIP 51OC/W 20-Lead PLCC 66OC/W

Ordering Information

Supertex inc. www.supertex.com Doc.# DSFP-HV9120 B060412

Electrical Characteristics

(Unless otherwise specified, VDD = 10V, +VIN = 48V, RBIAS = 390KΩ, ROSC = 330KΩ, TA = 25°C.) Sym Parameter # Min Typ Max Units Conditions Reference VREF Output voltage - 3.92 4.00 4.08 V RL = 10MΩ 3.84 4.00 4.16 RL = 10MΩ, TA = -55 to 125OC ZOUT Output impedance # 15 30 45 KΩ --- ISHORT Short circuit current - - 125 250 μA VREF = -VIN ΔVREF Change in VREF with temperature # - 0.25 - mV/°C TA = -55 to 125°C Oscillator fMAX Oscillator frequency - 1.0 3.0 - MHz ROSC = 0Ω fOSC Initial accuracy1 - 80 100 120 KHz ROSC = 330KΩ - 160 200 240 ROSC = 150KΩ ΔVOSC Voltage stability - - - 15 % 9.5V < VDD < 13.5V TCOSC Temperature coefficient # - 170 - ppm/°C TA = -55 to 125°C PWM DMAX Maximum duty cycle # 49.0 49.4 49.6 % --- DMIN Minimum duty cycle - - - 0 % --- Maximum pulse width before pulse drops out # - 80 125 ns --- Current Limit VLIM Maximum input signal - 1.0 1.2 1.4 V VFB = 0V tD Delay to output # - 80 120 ns VSENSE = 1.5V, VCOMP ≤ 2.0V Error Amplifier VFB Feedback voltage - 3.92 4.00 4.08 V VFB shorted to COMP IIN Input bias current - - 25 500 nA VFB = 4.0V VOS Input offset voltage - nulled during trim - --- AVOL Open loop voltage gain # 60 80 - dB --- GB Unity gain bandwidth # 1.0 1.3 - MHz --- ZOUT Out impedance # see Fig. 1 Ω --- ISOURCE Output source current - -1.4 -2.0 - mA VFB = 3.4V ISINK Output sink current - 0.12 0.15 - mA VFB = 4.5V PSRR Power supply rejection # see Fig. 2 dB --- Notes: # Guaranteed by design. 1. Stray capacitance on OSC In pin must be ≤5pF.

Supertex inc. www.supertex.com Doc.# DSFP-HV9120 B060412 Electrical Characteristics (cont.) (Unless otherwise specified, VDD = 10V, +VIN = 48V, RBIAS = 390KΩ, ROSC = 330KΩ, TA = 25°C.) Sym Parameter # Min Typ Max Units Conditions Pre-Regulator/Startup +VIN Input voltage - 10 - 450 V IIN < 10µA; VCC > 9.4V +IIN Input leakage current - - - 10 μA VDD > 9.4V VTH VDD pre-regulator turn-off threshold voltage - 8.0 8.7 9.4 V IPREREG = 10µA VLOCK Undervoltage lockout - 7.0 8.1 8.9 V --- Supply IDD Supply current - - 0.75 1.3 mA CL < 75pF IQ Quiescent supply current - - 0.55 - mA SHUTDOWN = -VIN IBIAS Nominal bias current - - 20 - μA --- VDD Operating range - 9.0 - 13.5 V --- Shutdown Logic tSD SHUTDOWN delay # - 50 100 ns CL = 500pF, VSENSE = -VIN tSW SHUTDOWN pulse width # 50 - - ns tRW RESET pulse width # 50 - - ns --- tLW Latching pulse width # 25 - - ns SHUTDOWN and RESET low VIL Input low voltage - - - 2.0 V --- VIH Input high voltage - 7.0 - - V --- IIH Input current, input high voltage - - 1.0 5.0 μA VIN = VDD IIL Input current, input low voltage - - -25 -35 μA VIN = 0V Output VOH Output high voltage - VDD -0.25 - - V IOUT = 10mA - VDD -0.3 - - V IOUT = 10mA, TA = -55 to 125°C VOL Output low voltage - - - 0.2 V IOUT = -10mA - - - 0.3 V IOUT = -10mA, TA = -55 to 125°C ROUT Output resistance Pull up - - 15 25 Ω IOUT = ±10mA Pull down - - 8.0 20 Ω Pull up - - 20 30 Ω IOUT = ±10mA, TA = -55 to 125°CPull down - - 10 30 Ω tR Rise time # - 30 75 ns CL = 500pF tF Fall time # - 20 75 ns CL = 500pF Note: # Guaranteed by design.

Supertex inc. www.supertex.com Doc.# DSFP-HV9120 B060412 Test Circuits Detailed Description Pre regulator The pre regulator/startup circuit for the HV9120 consists of a high-voltage n-channel depletion-mode DMOS transistor driven by an error amplifier to form a variable current path between the VIN terminal and the VDD terminal. Maximum current (about 20 mA) occurs when V DD = 0, with current re- ducing as VDD rises. This path shuts off altogether when VDD rises to somewhere between 7.8 and 9.4V, so that if V DD is held at 10 or 12V by an external source (generally the sup- ply the chip is controlling), no current other than leakage is drawn through the high voltage transistor. This minimizes dissipation. An external capacitor between VDD and VSS is generally required to store energy used by the chip in the time be- tween shutoff of the high voltage path and the VDD supply’s output rising enough to take over powering the chip. This capacitor should have a value of 100X or more the effective gate capacitance of the MOSFET being driven, i.e., C STORAGE ≥ 100 x (gate charge of FET at 10V) as well as very good high frequency characteristics. Stacked polyester or ceramic caps work well. Electrolytic capacitors are generally not suitable. A common resistor divider string is used to monitor V DD for both the undervoltage lockout cir- cuit and the shutoff circuit of the high voltage FET. Setting the undervoltage sense point about 0.6V lower on the string than the FET shutoff point guarantees that the undervoltage lockout always releases before the FET shuts off. Bias Circuit An external bias resistor, connected between the bias pin and VSS is required by the HV9120 to set currents in a se- ries of current mirrors used by the analog sections of the chip. Nominal external bias current requirement is 15 to 20µA, which can be set by a 390 to 510KΩ resistor if a 10V V DD is used, or a 510 to 680KΩ resistor if V DD will be 12V. A precision resistor is not required; ±5% is fine. Clock Oscillator The clock oscillator of the HV9120 consists of a ring of CMOS inverters, timing capacitors, a capacitor discharge FET, and a frequency dividing flip-flop. A single external re- sistor between the OSC IN and OSC OUT pins is required to set oscillator frequency (see graph). One difference exists between the Supertex HV9120 and competitive 9120s: The oscillator is shut off when a shutoff command is received. This saves about 150µA of quiescent current, which aids in the construction of power supplies to meet CCITT specification I-430, and in other situations where an absolute minimum of quiescent power dissipation is required. Reference The Reference of the HV9120 consists of a stable bandgap reference followed by a buffer amplifier which scales the voltage up to approximately 4.0V. The scaling resistors of the reference buffer amplifier are trimmed during manufac- ture so that the output of the error amplifier, when connected in a gain of -1 configuration, is as close to 4.0V as possible. This nulls out any input offset of the error amplifier. As a con- sequence, even though the observed reference voltage of a specific part may not be exactly 4.0V, the feedback voltage required for proper regulation will be. A ≈ 50KΩ resistor is placed internally between the output of the reference buffer amplifier and the circuitry it feeds (reference output pin and non-inverting input to the error amplifier). This allows overriding the internal reference with a low-impedance voltage source ≤6.0V. Using an external reference reinstates the input offset voltage of the error am- plifier, and its effect of the exact value of feedback voltage 60.4K 40.2K 1.0V swept 100Hz - 2.2MHz Tektronix P6021 (1 turn secondary) 0.1µF +10V (VDD) GND (-VIN) (FB) Error Amp ZOUT Reference V2 10.0V 4.0V 100K1% 100K 1% PSRR 0.1µF 0.1V swept 10Hz - 1.0MHz V2 V1 Reference Note: Set feedback voltage so that VCOMP = VDIVIDE ± 1.0mV before connecting transformer.

Supertex inc. www.supertex.com Doc.# DSFP-HV9120 B060412 required. In general, because the reference voltage of the Supertex HV9120 is not noisy, as some previous examples have been, overriding the reference should seldom be nec- essary. Because the reference of the HV9120 is a high impedance node, and usually there will be significant electrical noise near it, a bypass capacitor between the reference pin and VSS is strongly recommended. The reference buffer ampli - fier is intentionally compensated to be stable with a capaci - tive load of 0.01 to 0.1µF. Error Amplifier The error amplifier in the HV9120 is a true low-power dif- ferential input operational amplifier intended for around-the- amplifier compensation. It is of mixed CMOS-bipolar con- struction: A PMOS input stage is used so the common-mode range includes ground and the input impedance is very high. This is followed by bipolar gain stages which provide high gain without the electrical noise of all-MOS amplifiers. The amplifier is unity-gain stable. Current Sense Comparators The HV9120 uses a true dual-comparator system with in- dependent comparators for modulation and current limiting. This allows the designer greater latitude in compensation design, as there are no clamps (except ESD protection) on the compensation pin. Like the error amplifier, the compara- tors are of low-noise BiCMOS construction. Remote Shutdown The SHUTDOWN and RESET pins of the HV9120 can be used to perform either latching or non-latching shutdown of a converter as required. These pins have internal current source pull-ups so they can be driven from open-drain logic. When not used, they should be left open or connected to VDD. Output Buffer The output buffer of the HV9120 is of standard CMOS con- struc-tion (P-channel pull-up, N-channel pull-down). Thus the body-drain diodes of the output stage can be used for spike clipping if necessary, and external Schottky diode clamping of the output is not required. SHUTDOWN RESET Output H H Normal operation H H → L Normal operation, no change L H Off, not latched L L Off, latched L → H L Off, latched, no change Truth Table Shutdown Timing Waveforms 50% tD 1.5V SENSE tSD 50% 90% 90% VDD SHUTDOWN tLW 50% 50% tSW 50% 50% tRW 50% tR ≤ 10ns tF ≤ 10ns tR, tF ≤ 10ns VDD SHUTDOWN VDD RESET VDD OUTPUT VDD OUTPUT

Supertex inc. www.supertex.com Doc.# DSFP-HV9120 B060412 Typical Performance Curves Output Switching Frequency vs. Oscillator Resistance 10k 100k 1M R OSC (Ω) f OUT (Hz) 100k 10k PSRR - Error Amplifier and Reference 10 100 1K 10K 100K 1M -10 Error Amplifier Open Loop Gain/Phase Gain (dB) Phase ( O C) 180 120 -60 -120 -180 Frequency (Hz) 10 6 10 5 10 4 10 3 10 2 1.0 0.1 Error Amplifier Output Impedance (Z0) -10 -20 -30 -40 -50 -60 -70 -80 Bias Resistance (Ω) 10 5 10 6 10 7 Bias Current (µA) V DD = 10V PSRR (dB) Frequency (Hz) Z 0 (Ω) 100 1K 10K 100K 1M 10M Frequency (Hz) V DD = 10V 100 1K 10K 100K 1M 100 1.0

Supertex inc. www.supertex.com Doc.# DSFP-HV9120 B060412 Pin Descriptions Pin # Description 1 NC 2 NC 3 +VIN 4 NC

5 SENSE

6 OUTPUT

9 VDD

10 OSC OUT

Pin # Description

11 OSC IN

14 VREF

16 SHUTDOWN

17 RESET

18 COMP

20 BIAS

Pin # Description 1 +VIN 2 - 3 -

4 SENSE

5 OUTPUT

7 VDD

8 OSC OUT

Pin # Description

9 OSC IN

11 VREF

12 SHUTDOWN

13 RESET

14 COMP

16 BIAS

16-Lead SOIC (NG) 16-Lead PDIP (P) 20-Lead PLCC (PJ) Pin # Description 1 +VIN 2 NC 3 NC Pin # Description

Supertex inc. www.supertex.com Doc.# DSFP-HV9120 B060412 16-Lead SOIC (Narrow Body) Package Outline (NG) 9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1 Dimension (mm) 1.27 BSC 0.25 0.40 1.04 REF 0.25 BSC 0O 5O JEDEC Registration MS-012, Variation AC, Issue E, Sept. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-16SONG, Version G041309. D Seating Plane Gauge Plane L Top View Side View View A-A View B View B θ E1 E A A2 A A Seating Plane e b h h Note 1 Note 1 (Index Area D/2 x E1/2) Note: 1. This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.

Supertex inc. www.supertex.com Doc.# DSFP-HV9120 B060412 16-Lead PDIP (.300in Row Spacing) Package Outline (P) .790x.250in body, .210in height (max), .100in pitch Note 1 (Index Area) D L A1 A A2 Seating Plane e D1D1 E A A Side View Top View View A - A eA eB b View B View B Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol A A1 A2 b b1 D D1 E E1 e eA eB L Dimension (inches) .100 BSC .300 BSC .300* .115 JEDEC Registration MS-001, Variation AB, Issue D, June, 1993. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-16DIPP, Version C021312.

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

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Tel: 408-222-8888 www.supertex.com (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) HV9120 Doc.# DSFP-HV9120 B060412 20-Lead PLCC Package Outline (PJ) .353x.353in body, .180in height (max), .050in pitch Symbol A A1 A2 b b1 D D1 E E1 e R Dimension (inches) .050 BSC .025 JEDEC Registration MS-018, Variation AA, Issue A, June, 1993. Drawings not to scale. Supertex Doc. #: DSPD-20PLCCPJ, Version C031111 .150 MAX .048/.042 x 45O .075 MAX D E1 E Top View View B A A2 A1 Seating Plane e Note 1 (Index Area) .056/.042 x 45O Base Plane .020 MIN b View B Horizontal Side View Vertical Side View Note 2 .020max (3 Places) R Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary.