HV9113NG-G

HV9113_07 SUTEX | Alldatasheet

Document overview

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Technical content

Features

► 10V to 120V Input Voltage Range ► Current-mode control ► High effi ciency ► Up to 1.0MHz internal oscillator ► Internal start-up circuit ► Low internal noise

Applications

► DC/DC converters ► Distributed power systems ► ISDN equipment ► PBX systems ► Modems General Description The Supertex HV9113 is a BiCMOS/DMOS single-output, pulse width modulator IC intended for use in high-speed, high-effi ciency switch mode power supplies. It provides all the functions necessary to implement a single-switch current mode PWM, in any topology, with a minimum of external parts. Because the HV9113 utilizes Supertex’s proprietary BiCMOS/ DMOS technology, it requires less than one tenth of the operating power of conventional bipolar PWM ICs, and can operate at more than twice their switching frequency. The dynamic range for regulation is also increased, to approximately 8 times that of similar bipolar parts. It starts directly from any DC input voltage between 10 and 120VDC, requiring no external power resistor. The output stage is push-pull CMOS and thus requires no clamping diodes for protection, even when signifi cant lead length exists between the output and the external MOSFET. The clock frequency is set with a single external resistor. Accessory functions are included to permit fast remote shutdown (latching or nonlatching) and under voltage shutdown. For similar ICs intended to operate directly from up to 450VDC input, please consult the data sheets for the HV9120 and HV9123. For detailed circuit and application information, please refer to application notes AN-H13 and AN-H21 to AN-H24. High-Voltage Current-Mode PWM Controller

Ordering Information

14-Lead Narrow Body SOIC (NG) HV9113 HV9113NG-G Absolute Maximum Ratings Parameter Value Input voltage, VIN 120V Logic voltage, VDD 15.5V Logic linear input, FB and sense input voltage -0.3V to VDD +0.3V Storage temperature -65°C to +150°C Power dissipation 750mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifi cations is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. -G indicates package is RoHS compliant (‘Green’) Pin Confi guration Product Marking Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking HV9113NG YWW LLLLLLLL CCCCCCCCC AAA 14-Lead Narrow Body SOIC (NG) 14-Lead Narrow Body SOIC (NG)

Electrical Characteristics

(Unless otherwise specifi ed, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ, TA = 25°C.) Sym Parameter # Min Typ Max Units Conditions Reference VREF Output voltage - 3.92 4.00 4.08 V RL = 10MΩ - 3.82 4.00 4.16 RL = 10MΩ TA = -55°C to 125°C ZOUT Output impedence # 15 30 45 KΩ --- ISHORT Short circuit current - - 125 250 μA V REF = -VIN ΔVREF Change in VREF with temperature # - 0.25 - mV/°C T A = -55°C to 125°C Oscillator fMAX Oscillator frequency - 1.0 3.0 - MHz R OSC = 1.0MΩ fOSC Initial accuracy(1) - 80 100 120 KHz ROSC = 330KΩ - 160 200 240 R OSC = 150KΩ - Voltage stability - - - 15 % V SYNC = 0.1V - Temperature coeffi cient # - 170 - ppm/°C T A = -55°C to 125°C PWM DMAX Maximum duty cycle - 95 97 99 % --- DMIN Deadtime # - 225 - ns --- Minimum duty cycle - - - 0 % --- Maximum pulse width before pulse drops out # - 80 125 ns --- Current Limit Maximum input signal - 1.0 1.2 1.4 V V FB = 0V tD Delay to output # - 80 120 ns VSENSE = 1.5V, VCOMP ≤ 2.0V Error Amplifi er VFB Feedback voltage - 3.96 4.00 4.04 V V FB shorted to comp IIN Input bias current - - 25 500 nA V FB = 4.0V VOS Input offset voltage - nulled during trim - --- AVOL Open loop voltage gain # 60 80 - dB --- GB Unity gain bandwidth # 1.0 1.3 - MHz --- ZOUT Out impedance # see Fig. 1 Ω --- ISOURCE Output source current - -1.4 -2.0 - mA V FB = 3.4V ISINK Output sink current - 0.12 0.15 - mA V FB = 4.5V PSRR Power supply rejection # see Fig. 2 dB --- Notes: # Guaranteed by design. Not subject to production test. (1) Stray capacitance on OSC In pin must be ≤5pF.

Electrical Characteristics (cont.) (Unless otherwise specifi ed, VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ, TA = 25°C.) Sym Parameter # Min Typ Max Units Conditions Pre-regulator/Startup +VIN Input voltage - 10 - 120 V I IN < 10µA; VCC > 9.4V +IIN Input leakage current - - - 10 μA V DD > 9.4V VTH Vdd pre-regulator turn-off threshold voltage - 8.0 8.7 9.4 V I PREREG = 10µA VLOCK Undervoltage lockout - 7.0 8.1 8.9 V --- Supply IDD Supply current - - 0.75 1.0 mA C L < 75pF IQ Quiescent supply current - - 0.55 - mA Shutdown = -V IN IBIAS Nominal Bias current - - 20 - μA --- VDD Operating range - 9.0 - 13.5 V --- Shutdown Logic tSD Shutdown delay # - 50 100 ns C L = 500pF, VSENSE = -VIN tSW Shutdown pulse width # 50 - - ns tRW RESET pulse width # 50 - - ns --- tLW Latching pulse width # 25 - - ns Shutdown and reset low VIL Input low voltage - - - 2.0 V --- VIH Input high voltage - 7.0 - - V --- IIH Input current, input high voltage - - 1.0 5.0 μA V IN = VDD IIL Input current, input low voltage - - -25 -35 μA V IN = 0V Output VOH Output high voltage -V DD - 0.25 - - V I OUT = 10mA -V DD - 0.3 - - V IOUT = 10mA, TA = -55°C to 125°C VOL Output low voltage - - - 0.2 V I OUT = -10mA - - - 0.3 V IOUT = -10mA, TA = -55°C to 125°C ROUT Output resistance Pull up - - 15 25 Ω IOUT = ±10mA Pull down - - 8.0 20 Ω Pull up - - 20 30 Ω IOUT = ±10mA, TA = -55°C to 125°CPull down - - 10 30 Ω tR Rise time # - 30 75 ns C L = 500pF tF Fall time # - 20 75 ns C L = 500pF Notes: # Guaranteed by design. Not subject to production test.

H H → L Normal operation, no change L H Off, not latched L L Off, latched L → H L Off, latched, no change Truth Table Shutdown Timing Waveforms Functional Block Diagram VDD 50% t d Output Sense 1.5V tSD 50% 90%90% VDD Output Shutdown VDD t LW 50% 50% tSW 50% 50% t RW Reset VDD Shutdown VDD 50% tR, tF ≤ 10ns tF ≤ 10ns tR ≤ 10ns REF GEN Modulator Comparator OSC R S Q Current Limit Comparator COMP Discharge OSC IN OSC OUTFB VREF BIAS VDD +VIN Pre-regulator/Startup 8.6V 8.1V Undervoltage Comparator S R Q VDD Shutdown Reset -VIN Current Sense Output Error Amplifier To Internal Circuits 1.2VCurrent Sources To VDD2V TQ 4 (6) 5 (8) 3 (5) 11 (16) 12 (17) 2 (3) 6 (9) 1 (20) 10 (14) (19) (18) (12) 8 (11) 7 (10)

Typical Performance Curves PSRR — Error Amplifier and Reference 1M10K100 100K 1K10 Output Switching Frequency vs. Oscillator Resistance 1M100 k10k 10k ROSC (Ω) )zH( f TUO -10 100 1K 10K Error Amplifier Open Loop Gain/Phase 100K 1M )Bd( niaG ( esahP ° )C 180 120 -60 -120 -180 Frequency (Hz) 106 105 104 103 102 10MHz1MHz100Hz 1KHz 10KHz Error Amplifier Output Impedance (Z0) 100KHz -10 -20 -30 -40 -50 -60 -70 -80 100k Bias Resistance (Ω) 107106105 ( tnerruC saiB µ )A 100 VDD = 10V VDD = 12V )Bd( RSSP Frequency (Hz) ZO ( Ω) Frequency RDISCHARGE vs. tOFF (9113 only) RDISCHARGE (Ω) 10310-1 102 t FFO )cesn( 103 104 ROSC = 1 00K ROSC = 1 0K ROSC = 1K 104100 105101 106102 Fig. 1 Fig. 2 Fig. 5 Fig. 3 Fig. 4 Fig. 6

The preregulator/startup circuit for the HV9113 consists of a high-voltage n-channel depletion-mode DMOS transis- tor driven by an error amplifi er to form a variable current path between the VIN terminal and the VDD terminal. The maximum current (about 20 mA) occurs when V DD = 0, with current reducing as VDD rises. This path shuts off altogether when VDD rises to somewhere between 7.8 and 9.4V, so that if VDD is held at 10 or 12V by an external source(generally the supply the chip is controlling). No current other than leakage is drawn through the high voltage transistor. This minimizes dissipation. An external capacitor between VDD and VSS is generally required to store energy used by the chip in the time be- tween shutoff of the high voltage path and the VDD supply’s output rising enough to take over powering the chip. This capacitor should have a value of 100X or more the effective gate capacitance of the MOSFET being driven, i.e., C STORAGE ≥ 100 x (gate charge of FET at 10V ÷ 10V) as well as very good high frequency characteristics. Stacked polyester or ceramic caps work well. Electrolytic capacitors are generally not suitable. A common resistor divider string is used to monitor V DD for both the under voltage lockout circuit and the shutoff circuit of the high voltage FET. Setting the under voltage sense point about 0.6V lower on the string than the FET shutoff point guarantees that the under voltage lockout always re- leases before the FET shuts off. Bias Circuit An external bias resistor, connected between the BIAS pin and VSS is required by the HV9113 to set currents in a se- ries of current mirrors used by the analog sections of the chip. The nominal external bias current requirement is 15 to 20µA, which can be set by a 390KΩ to 510KΩ resistor if a 10V V DD is used, or a 510kΩ to 680KΩ resistor if VDD will be 12V. A precision resistor is not required; ± 5% is fi ne. Clock Oscillator The clock oscillator of the HV9113 consists of a ring of CMOS inverters, timing capacitors, a capacitor discharge FET, and, in the 50% maximum duty cycle versions, a frequency divid- ing fl ip-fl op. A single external resistor between the OSC IN and OSC OUT is required to set the oscillator frequency (see graph). For the 50% maximum duty cycle versions the Dis- charge pin is internally connected to GND. For the 99% duty cycle version, the Discharge pin can either be connected to VSS directly or connected to VSS through a resistor used to set a deadtime. One major difference exists between the Supertex HV9113 and competitive 9110’s. On the Supertex part, the oscillator is shut off when a shutoff command is re- ceived. This saves about 150µA of quiescent current, which aids in the construction of power supplies that meet CCITT specifi cation I-430, and in other situations where an abso- lute minimum of quiescent power dissipation is required. Reference 0.1V swept 10Hz – 1MHz 0.1µF 10.0V 4.00V 100K1% 100K1% PSRR Reference V1 V2 60.4K 40.2K 1.0V swept 100Hz – 2.2MHz Tektronix P6021 (1 turn secondary) 0.1µF +10V (VDD) GND (–VIN) (FB) NOTE: Set Feedback Voltage so that VCOMP = VDIVIDE ± 1mV before connecting transformer Error Amp ZOUT

The Reference of the HV9113 consists of a stable bandgap reference followed by a buffer amplifi er which scales the voltage up to approximately 4.0V. The scaling resistors of the reference buffer amplifi er are trimmed during manufac- ture so that the output of the error amplifi er, when connected in a gain of –1 confi guration, is as close to 4.0V as possible. This nulls out any input offset of the error amplifi er. As a con- sequence, even though the observed reference voltage of a specifi c part may not be exactly 4.0V, the feedback voltage required for proper regulation will be. A ≈ 50KΩ resistor is placed internally between the output of the reference buffer amplifi er and the circuitry it feeds (refer- ence output pin and non-inverting input to the error ampli- fi er). This allows overriding the internal reference with a low impedance voltage source ≤6.0V. Using an external refer- ence reinstates the input offset voltage of the error amplifi er, and its effect of the exact value of feedback voltage required. Because the reference of the HV9113 is a high impedance node, and usually there will be signifi cant electrical noise near it, a bypass capacitor between the reference pin and VSS is strongly recommended. The reference buffer ampli- fi er is intentionally compensated to be stable with a capaci- tive load of 0.01 to 0.1µF. Error Amplifi er The error amplifi er in the HV9113 is a true low-power dif- ferential input operational amplifi er intended for around the amplifi er compensation. It is of mixed CMOS-bipolar con- struction: A PMOS input stage is used so the common mode range includes ground and the input impedance is very high. This is followed by bipolar gain stages which provide high gain without the electrical noise of all-MOS amplifi ers. The amplifi er is unity gain stable. Current Sense Comparators The HV9113 uses a true dual comparator system with in- dependent comparators for modulation and current limiting. This allows the designer greater latitude in compensation design, as there are no clamps (except ESD protection) on the compensation pin. Like the error amplifi er, the compara- tors are of low-noise BiCMOS construction. Remote Shutdown The shutdown and reset pins of the 9110 can be used to perform either latching or non-latching shutdown of a con- verter as required. These pins have internal current source pull-ups so they can be driven from open drain logic. When not used they should be left open, or connected to VDD. Output Buffer The output buffer of the HV9113 is of standard CMOS con- struction (P-channel pull-up, N-channel pull-down). Thus the body-drain diodes of the output stage can be used for spike clipping if necessary, and external Schottky diode clamping of the output is not required.

(The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV9113 A101007 14-Lead SOIC (Narrow Body) Package Outline (NG) 8.65x3.90mm body, 1.27mm pitch Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1 Dimension (mm) 1.27 BSC 0.25 0.40 1.04 REF 0.25 BSC 0O 5O JEDEC Registration MS-012, Variation AB, Issue E, Sept. 2005. Drawinngs not to scale. D Seating Plane Gauge Plane L Top View Side View View A-A View B View B θ E1 E A A2 A A Seating Plane e b h h Note 1 (Index Area D/2 x E1/2) Note 1 Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifi er must be located in the index area indicated.The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature.