HV9100

HV9100 SUTEX | Alldatasheet

Document overview

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Technical content

Features

❏ 10 to 120V input range ❏ 200V, 7.0Ω output MOSFET ❏ Current-Mode Control ❏ High Efficiency ❏ Up to 1MHz Internal Oscillator ❏ Internal Start-up Circuit +VIN Feedback Max MOSFET Switch Package Options Min Max Voltage Duty Cycle BVDSS RDS (ON) 14 Pin Plastic DIP 20 Pin Plastic PLCC 10V 70V ± 1.0% 49% 150V 5.0 Ω HV9100P HV9100PJ 10V 120V ± 1.0% 49% 200V 7.0 Ω HV9102P HV9102PJ 10V 120V ±1.0% 99% 200V 7.0 Ω HV9103P HV9103PJ Standard temperature range for all parts is industrial (-40° to +85°C).

Ordering Information

High-Voltage Switchmode Controllers with MOSFET For detailed circuit and application information, please refer to application notes AN-H13 and AN-H21 to AN-H24. HV9100 HV9102 HV9103 11/12/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liabi lity to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to c hange without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most curre nt databook or to the Legal/Disclaimer page on the Supertex website.

Electrical Characteristics

(VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ,TA = 25°C, unless otherwise specified) Symbol Parameters Min Typ Max Unit Conditions Reference VREF Output Voltage HV9100/02/03 3.92 4.00 4.08 V R L = 10MΩ HV9102/03 3.86 4.00 4.14 V IN = V IN, RL = 10MΩ TA = -55°C to 125°C ZOUT Output Impedance1 15 30 45 K Ω ISHORT Short Circuit Current 100 250 µAV REF = -VIN ∆VREF Change in VREF with Temperature 0.25 mV/ °C Oscillator fMAX Oscillator Frequency 1.0 3.0 MHz R OSC = 0Ω fOSC Initial Accuracy2 80 100 120 KHz R OSC = 330KΩ 160 200 240 R OSC = 150KΩ Voltage Stability 15 % 9.5V < V DD < 13.5V Temperature Coefficient 170 ppm/ °C PWM DMAX Maximum Duty Cycle HV9100/02 49.0 49.4 49.6 % HV9103 99.0 99.4 99.6 Deadtime HV9103 100 nsec DMIN Minimum Duty Cycle 0 % Minimum Pulse Width 110 175 nsec Before Pulse Drops Out 1 Error Amplifier VFB Feedback Voltage HV9100/02/03 3.96 4.00 4.04 V V FB Shorted to Comp IIN Input Bias Current 25 500 nA V FB = 4.0V VOS Input Offset Voltage nulled at trim mV Except 9101 AVOL Open Loop Voltage Gain1 60 80 dB gbw Unity Gain Bandwidth 1 1.0 1.3 MHz ZOUT Output Impedance1 See Fig. 2 Ω ISOURCE Output Source Current -2.0 -1.4 mA V FB = 3.4V ISINK Output Sink Current 0.12 0.15 mA V FB = 4.5V PSRR Power Supply Rejection See Fig. 1 Current Limit VSOURCE Threshold Voltage 1.0 1.2 1.4 V V FB = 0V, RL = 100Ω td Delay to Output1 150 ns V SOURCE = 1.5V, RL = 100Ω Notes: 1. Guaranteed by design. Not subject to production test. 2. Stray capacitance on OSC In pin ≤5pF .

Electrical Characteristics (Continued) (VDD = 10V, +VIN = 48V, Discharge = -VIN = 0V, RBIAS = 390KΩ, ROSC = 330KΩ,TA = 25°C, unless otherwise specified) Symbol Parameters Min Typ Max Unit Conditions Pre-Regulator/Startup +VIN Allowable Input Voltage HV9100 70 V I IN = 10µA HV9102/03 120 Input Leakage Current 10 µAV DD > 9.4V VTH VDD Pre-regulator Turn-off 7.8 8.6 9.4 V I PREREG = 10µA Threshold Voltage VLOCK Undervoltage Lockout 7.0 8.1 8.9 V R L = 100Ω from Drain to VDD Supply IDD Supply Current 0.60 1.0 mA 0.55 mA Shutdown = -V IN IBIAS Bias Current 20 µA VDD Operating Range 9.0 13.5 V Logic tSD Shutdown Delay Time1 50 100 ns V SOURCE = -VIN tSW Shutdown Pulse Width1 50 ns tRW RESET Pulse Width1 50 ns tLW Latching Pulse Width1 25 ns VIL Input Low Voltage 2.0 V VIH Input High Voltage 7.0 V IIH Input High Current 1.0 5.0 µAV IN = 10V IIL Input Low Current -25 -35 µAV IN = 0V MOSFET Switch BVDSS Breakdown Voltage HV9100 150 V V SOURCE = Shutdown = 0V, HV9102/03 200 I D = 100µA, TA = -55°C to 125°C RDS(ON) Drain-to-Source HV9100 3.5 5.0 Ω VSOURCE = 0V, ID = 100mA On-resistance HV9102/03 7.0 Ω IDSS OFF State Drain Leakage Current 10 µAV SOURCE = Shutdown = 0V, VDRAIN = 100V CDS Drain Capacitance 35 pF V DS = 25V, Shutdown = 0V Truth Table Shutdown Reset Output H H Normal Operation HH → L Normal Operation, No Change L H Off, Not Latched L L Off, Latched L → H L Off, Latched, No Change Note: 1. Guaranteed by design. Not subject to production test.

R S Q C/L Comparator COMP Discharge OSC In OSC OutFB VREF BIAS VDD +VIN Pre-regulator/Startup 8.6V 8.1V Undervoltage Comparator S R Q VDD Shutdown Reset Source Error Amplifier To Internal Circuits 1.2VCurrent Sources VDD Drain -V IN 9100 9102 TQ 9103 (20) 10 (14) (18) (12) (11) 7 (10) (5) 3 (8) 5 (7) 4 (16) 11 (17) 12 2 (3) 6 (9) 1 (2) Switching Waveforms Functional Block Diagram VDD 50% t d Drain Source 1.5V tSD 50% 90%90% VDD Drain Shutdown VDD t LW 50% 50% tSW 50% 50% t RW Reset VDD Shutdown VDD 50% tR, tF ≤ 10ns tF ≤ 10ns tR ≤ 10ns Pin numbers in parentheses are for PLCC pacage.

0.1V swept 10Hz – 1MHz 0.1µF 10.0V 4.00V 100K1% 100K1% PSRR Reference V1 V2 60.4K 40.2K 1.0V swept 100Hz – 2.2MHz Tektronix P6021 (1 turn secondary) 0.1µF +10V (VDD) GND (–VIN) (FB) NOTE: Set Feedback Voltage so that VCOMP = VDIVIDE ± 1mV before connecting transformer Error Amp ZOUT Output Switching Frequency vs. Oscillator Resistance 1M100 k10k 10k R OSC (Ω) f (Hz)OUT 100k HV9103 HV9100, 9101, 9102 Frequency -10 100Hz 1KHz 10KHz Error Amplifier Open Loop Gain/Phase 100KHz 1MHz Gain (dB) Phase 180° 120° 60° -60° -120° -180° 106 105 104 103 102 1.0 0.1 .01 10MHz1MHz100Hz 1KHz 10KHz Error Amplifier Output Impedance (Z0) 100KHz PSRR – Error Amplifier and Reference 100KHz1KHz -10 -20 -30 -40 -50 -60 -70 -80 10Hz 100Hz 10KHz 1MHz (dB)(Ω) Fig. 1 Fig. 2 Fig. 4 Fig. 3 Typical Performance Curves Test Circuits

The reference consists of a stable bandgap reference followed by a buffer amplifier which scales the voltage up to approximately 4.0V. The scaling resistors of the reference buffer amplifier are trimmed during manufacture so that the output of the error amplifier when connected in a gain of -1 configuration is as close to 4.000V as possible. This nulls out any input offset of the error amplifier. As a consequence, even though the observed refer- ence voltage of a specific part may not be exactly 4V, the feedback voltage required for proper regulation will be 4V. A resistor of approximately 50KΩ is placed internally between the output of the reference buffer amplifier and the circuitry it feeds (reference output pin and NON-INVERTING input to the error amplifier). This allows overriding the internal reference with a low- impedance voltage source ≤6V. Using an external reference reinstates the input offset voltage of the error amplifier, and its effect of the exact value of feedback voltage required. In general, because the reference voltage of the Supertex HV910x is not noisy, as some previous devices have been, overriding the reference should seldom be necessary. Because the reference is a high impedance node, and usually there will be significant electrical noise near it, a bypass capacitor between the reference pin and V SS is strongly recommended. The reference buffer amplifier is intentionally compensated to be stable with a capacitive load of 0.01 to 0.1µF. Error Amplifier The error amplifier is a true low-power differential input opera- tional amplifier intended for around-the-amplifier compensation. It is of mixed CMOS-bipolar construction: a PMOS input stage is used so the common-mode range includes ground and the input impedance is very high. This is followed by bipolar gain stages which provide high gain without the electrical noise of all-MOS amplifiers. The amplifier is unity-gain stable. Current Sense Comparators The HV910x uses a true dual comparator system with indepen- dent comparators for modulation and current limiting. This allows the designer greater latitude in compensation design, as there are no clamps (except ESD protection) on the compensation pin. Like the error amplifier, the comparators are of low-noise BiCMOS construction. Remote Shutdown The shutdown and reset pins can be used to perform either latching or non-latching shutdown of a converter as required. These pins have internal current source pull-ups so they can be driven from open-drain logic. When not used, they should be left open, or connected to V DD. Main Switch The main switch is a normal N-channel power MOSFET. Unlike the situation with competitive devices, the body diode can be used if desired without destroying the chip. Preregulator The preregulator/startup circuit for the HV910x consists of a high- voltage N-channel depletion-mode DMOS transistor driven by an error amplifier to form a controlled current path between the VIN terminal and the VDD terminal. Maximum current (about 20 mA) occurs when VDD = 0, with current reducing as VDD rises. This path shuts off altogether when VDD rises to somewhere between 7.8 and 9.4V, so that if VDD is held at 10 or 12V by an external source (generally the supply the chip is controlling) no current other than leakage is drawn through the high voltage transistor. This mini- mizes dissipation. An external capacitor between V DD and VSS is generally required to store energy used by the chip during the time between shutoff of the high voltage path and the VDD supply’s output rising enough to take over the powering of the chip. This capacitor generally also serves as the output filter capacitor for that output from the supply. 1µF is generally sufficient to assure against double-starting. Capacitors as small as 0.1µF can work when faster response from the V DD line is required. Whatever capacitor is chosen should have very good high frequency characteristics. Stacked polyester or ceramic capacitors work well. Electrolytic capacitors are gen- erally not suitable. A common resistor divider string is used to monitor V DD for both the undervoltage lockout circuit and the shutoff circuit of the high voltage FET. Setting the undervoltage sense point about 0.6V lower on the string than the FET shutoff point guarantees that the undervoltage lockout always releases before the FET shuts off. Bias Circuit An external bias resistor, connected between the bias pin and VSS is required to set currents in a series of current mirrors used by the analog sections of the chip. Nominal external bias current require- ment is 15 to 20 µA, which can be set by a 390K Ω to 510K Ω resistor if a 10V V DD is used, or a 510KΩ to 680KΩ resistor if a 12V VDD is used. A precision resistor is NOT required; ± 5% is fine. For extremely low power operation, the value of bias current can be reduced to as low as 5µA by further increases in the value of the bias resistor. This will reduce quiescent current by about a third, reduce bandwidth of the error amp by about half, and slow the current sense comparator by about 30%. Clock Oscillator The clock oscillator of the HV910x consists of a ring of CMOS inverters, timing capacitors, a capacitor discharge FET, and, in the 50% maximum duty cycle versions, a frequency dividing flip- flop. A single external resistor between the OSC In and OSC Out pins is required to set oscillator frequency (see Fig. 4). For the 50% maximum duty cycle versions the ‘Discharge’ pin is internally connected to GND. For the 99% duty cycle version, ‘Discharge’ can either be connected to V SS directly or connected to V SS through a resistor used to set a deadtime. One difference exists between the Supertex HV910x and com- petitive parts. The oscillator of the HV910x is shut off when a shutoff command is received. This saves about 150µA of quies- cent current, which aids in situations where an absolute minimum of quiescent power dissipation is required. Technical Description

+VIN NC Discharge OSC In OSC Out V DD NC Drain NC Source IN top view 20-pin PJ Package COMPReset Shutdown NC V REF Feedback COMP Reset Shutdown V REF Discharge OSC In BIAS IN Drain Source –VIN VDD OSC Out

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