HV7620_13 SUTEX | Alldatasheet
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Features
► HVCMOS® technology ► 5.0V logic and 12V supply rail ► Output voltage up to +200V ► Low power level shifting ► Source/sink current minimum 50mA ► 40MHz equivalent data rate ► Latched data outputs ► Forward and reverse shifting options (DIR pin) ► Chip select ► Polarity function Functional Block Diagram 40MHz, 32-Channel Serial to Parallel Converter with Push-Pull Outputs General Description The HV7620 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for color AC plasma displays. The device has 4 parallel 8-bit shift registers permitting data rates four times the speed of one. The data is clocked in simultaneously on all four data inputs with a single clock. Data is shifted in on a low to high transition of the clock. The latches and control logic perform the output enable function. The DIR pin causes clockwise (CW) shifting of the data when connected to VDD1, and counterclockwise (CCW) shifting when connected to LVGND. Operation of the shift register is not affected by the LE (latch enable) input. Transfer of data from the shift registers to the latches occurs when the LE input is high. Data is stored in the latches when LE is low. The current source on the logic inputs provides active pull up when the input pins are open. LE BLA CS POL CLK HVOUTA1 HVOUTB1 HVOUTC1 HVOUTD1 DINA DOUTA BLB DIR BLC BLD HVOUTA8 HVOUTB8 HVOUTC8 HVOUTD8 ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ DINB DOUTB DINC DOUTC DIND DOUTD QA1 8-Bit Latches QA8 QB1 8-Bit Latches QB8 QC1 8-Bit Latches QC8 8-Bit Shift Register 8-Bit Shift Register 8-Bit Shift Register 8-Bit Shift Register QD1 8-Bit Latches QD8
Supertex inc. www.supertex.com Doc.# DSFP-HV7620 C112213 Absolute Maximum Ratings Parameter Value Supply voltage, VDD1 -0.5V to +14V Supply voltage, VDD2 -0.5V to +14V Supply voltage, VPP -0.5V to +225V Logic input levels -2.0V to VDD1 + 2.0V Continuous total power dissipation1 1200mW Operating temperature range -40°C to +85°C Storage temperature range -65°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C. Recommended Operating Conditions Sym Parameter Min Max Units VDD1 Logic supply voltage 4.5 VDD2 V VDD2 12V supply voltage 10.8 13.2 V VPP High voltage supply voltage 50 200 V VIH High-level input voltage VDD1 -0.5V VDD1 V VIL Low-level input voltage 0 0.5 V fCLK Clock frequency VDD1 = 5.0V - 10 MHz VDD1 = 12V - 5 MHz TA Operating temperature range -40 +85 °C IOD Allowable pulsed current through output diodes1 - 500 mA IGND(VPP) Allowable pulsed VPP or HVGND current1 - 16 A VPP(SLEW) Slew rate of VPP - 340 V/µs Notes: 1. The current pulse width = 500ns, duty cycle = 5%. Pin Configuration Product Marking L = Lot Number YY = Year Sealed WW = Week Sealed C = Country of Origin A = Assembler ID = “Green” Packaging Top Marking HV7620PG LLLLLLLLLL YYWW CCCCCCCC AAA 64-Lead PQFP (3-sided) 64-Lead PQFP (3-sided) (top view) Package may or may not include the following marks: Si or Ordering Information / Availability Part Number Package Option Packing HV7620PG-G 64-Lead PQFP (3-sided) 66/tray Typical Thermal Resistance Package θja 64-Lead PQFP 41OC/W -G denotes a lead (Pb)-free / RoHS compliant package
Supertex inc. www.supertex.com Doc.# DSFP-HV7620 C112213 (Over operating supply voltages and temperature, unless otherwise noted, VDD1 = 5.0V, VDD2 = 12V, VPP = 200V and Tj = 25°C) Sym Parameter Min Max Units Conditions IDD1 VDD1 supply current - 5.0 mA fCLK = 10MHz IDD2 VDD2 supply current - 20 mA VDD2 = 13.2V, fCLK = 10MHz IPP High voltage supply current - 2.0 mA All outputs high or low IDD1Q Quiescent VDD1 supply current - 100 µA All input = VDD1 IDD2Q Quiescent VDD2 supply current - 100 µA All input = VDD1 VOH High-level output HVOUT 185 - V IO = -50mA Data OUT VDD -1 - IO = -100µA VOL Low-level output HVOUT - 20 V IO = +50mA Data OUT - 1.0 IO = +100µA IIH High-level logic input current - 1.0 µA VIN = VDD1 IIL Low-level logic input current - -10 µA VIN = 0V VGG HVGND to LVGND voltage difference -1.0 1.0 V --- (Logic signal inputs and data inputs have tr, tf ≤ 5ns. VDD1 = 5.0V or 12V, VDD2 = 12V, VPP = 200V and Tj = 25°C) Sym Parameter Min Max Units Conditions fCLK Clock frequency VDD1 = 5.0V - 10 MHz Per register, CL = 15pF VDD1 = 12V - 5.0 tWL, tWH Clock width high or low 40 - ns --- tSU Data set-up time before clock rises 20 - ns --- tH Data hold time after clock rises 20 - ns --- tON, tOFF Time from latch enable to HVOUT - 275 ns CL = 15pF tWLE LE pulse width 25 - ns --- tDLE Delay time clock to LE low to high 50 - ns --- tSLE LE set-up time before clock rises 20 - ns --- tDLF, tDLN BL or CS low to high to HVOUT - 250 ns --- tCOF, tCON Clock to HVOUT - 275 ns --- tDLH Delay time clock to data low to high VDD1 = 5.0V - 250 ns CL = 15pF VDD1 = 12V - 100 tDHL Delay time clock to data high to low V DD1 = 5.0V - 250 ns CL = 15pF VDD1 = 12V - 100
Supertex inc. www.supertex.com Doc.# DSFP-HV7620 C112213 Input and Output Equivalent Circuits Switching Waveforms VDD1 INPUT Logic Inputs VDD1 VPP HVOUT VDD2 LVGND LVGND HVGND DATA OUT Logic Data Output High Voltage Outputs CLK Data Input 50% 50% 50% 50% tSU tH tWL tf tWH tr 90% 10% 50% 90% 10% 50% tDLE tWLE tSLE 10% 90% tOFF LE tON VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL HVOUT HVOUT 50% 50% 50% 50% tDHL tCOF tCON tDLH Data Valid VOH VOL VOH VOL Data Output 10% tDLF 90% tDLN VIH VIL VOH VOL BLA, BLB, BLC, BLD, or CS HVOUT 50%
Supertex inc. www.supertex.com Doc.# DSFP-HV7620 C112213 Function Table Function Inputs HVOUT DINA DINB DINC DIND CLK LE DIR BLA BLB BLC BLD CS POL A B C D All O/P High X X X X X X X X X X X L L H H H H All O/P Low X X X X X X X X X X X L H L L L L “A”† Outputs Low X X X X X X X L X X X X H L * * * Normal Polarity X X X X X X X H H H H H H No Inversion Outputs Inverted X X X X X X X H H H H H L Inversion Transparent Mode H L L L ↑ H X H H H H H H H L L L Data Stored X X X X X L X H H H H H H Stored data Shift CWA X X X X ↑ H H H H H H H X AN AN+1 BN BN+1 CN CN+1 DN DN+1 Shift CCWB X X X X ↑ H L H H H H H X AN AN-1 BN BN-1 CN CN-1 DN DN-1 Notes: H = High level, L = Low level, X = Irrelevant, ↑ = Low to high transition. * = Dependent on previous stage’s state before the last CLK ↑ for last LE high. † = BLB, BLC and BLD will have similar effect on their respective output. Power-up sequence: 1. GND (HV, LV) 2. V DD1 3. VDD2 4. VPP 5. Logic Input Signals To power down reverse the sequence above.
Supertex inc. www.supertex.com Doc.# DSFP-HV7620 C112213 Pin Function Pin # Function
1 HVGND
2 VPP
3 HVOUTD8
4 HVOUTC8
5 HVOUTB8
6 HVOUTA8
7 HVOUTD7
8 HVOUTC7
9 HVOUTB7
10 HVOUTA7
11 HVOUTD6
12 HVOUTC6
13 HVOUTB6
14 HVOUTA6
15 HVOUTD5
16 HVOUTC5
Pin # Function
17 HVOUTB5
18 HVOUTA5
19 VPP
20 HVGND
21 HVGND
22 VDD2
23 BLC
24 BLD
26 DOUTD
27 DIND
28 DINC
29 DOUTC
30 POL
31 LVGND
32 DIR
Pin # Function 33 CS
34 DOUTB
35 DINB
36 DINA
37 DOUTA
38 CLK
39 BLA
40 BLB
41 VDD1
42 LVGND
43 N/C
44 HVGND
45 HVGND
46 VPP
47 HVOUTD4
48 HVOUTC4
Pin # Function
49 HVOUTB4
50 HVOUTA4
51 HVOUTD3
52 HVOUTC3
53 HVOUTB3
54 HVOUTA3
55 HVOUTD2
56 HVOUTC2
57 HVOUTB2
58 HVOUTA2
59 HVOUTD1
60 HVOUTC1
61 HVOUTB1
62 HVOUTA1
63 VPP
64 HVGND
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888 www.supertex.com HV7620 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV7620 C112213 64-Lead PQFP (3-Sided) Package Outline (PG) Symbol A A1 A2 b D D1 E E1 e L L1 L2 L3 θ θ1 Dimen- sion (mm) 0.80 BSC 0.73 1.95 REF 0.25 BSC 0.55 REF 0O 5O Drawings not to scale. Supertex Doc. #: DSPD-64PQFPPG, Version A080812. Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. The leads on this side are trimmed. View BSide View Top View Note 1 (Index Area D1/4 x E1/4) Note 2 Seating Plane Gauge Plane θ L View B Seating Plane A2A D EE1 b e θ1