HV758

HV758 SUTEX | Alldatasheet

Document overview

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Technical content

Features

HVCMOS technology for high performance High density integration ultrasound transmitter 0 to ±90V output voltage ±2.2A source and sink current in PW mode ±580mA source and sink current in CW mode Up to 20MHz operating frequency Matched delay times 1.2V to 5.0V CMOS logic interface Built-in output drain bleed resistors Application Medical ultrasound imaging Piezoelectric transducer drivers NDT ultrasound transmission Pulse waveform generator General Description The Supertex HV758 is a four-channel, monolithic high voltage, high-speed pulse generator. It is designed for medical ultrasound applications. This high voltage and high-speed integrated circuit can also be used for other piezoelectric, capacitive or MEMS transducers in ultrasonic nondestructive detection and sonar ranger applications. The HV758 comprises a controller logic interface circuit, level translators, MOSFET gate drives and high current power P- channel and N-channel MOSFETs as the output stage for each channel. The output current limit can be set to one of four levels by using two mode control inputs. The output stages of each channel are designed to provide peak output currents over ±2.5A when in mode 4, with up to 180V swings. When in mode 1, the output stages reduce the peak current to ±580mA for CW mode operation, which reduces the power dissipation of the IC. The power MOSFET gate drivers are supplied by two fl oating 10VDC power supplies referenced to V PP and VNN. This direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the PCB layout easier. Typical Application Circuit Quad High Speed ±90V 2.2A Ultrasound Pulser NIN1 SUB VPP -10V VPFVDD +10V GREF VPP 0 to +90V EN MC1 VNN 0 to -90V TXN1 VNN +10V 1 of 4 Channels C2 C3 C5C4 TXP1 HVOUT1 VNF VSUBVLL +1.8 to 3.3V +90V C6C7 EN_PWR MC0 OTP VSS PIN1 RP1 RN1 RGND +1.8 to 3.3V Logic HV758 RGND P-Driver N-Driver Level Translator Level Translator

Ordering Information

8x8mm body, 2.45mm height (max), 0.8mm pitch HV758 HV758FB HV758FB-G Absolute Maximum Ratings Parameter Value VSS, Power supply reference 0V VLL, Positive logic supply -0.5V to +7.0V VDD, Positive logic and level translator supply -0.5V to +14V (VPP - VPF) Positive fl oating gate drive supply -0.5V to +14V (VNF - VNN) Negative gate fl oating drive supply -0.5V to +14V (VPP - VNN) Differential high voltage supply +190V VPP, High voltage positive supply -0.5V to +95V VNN, High voltage negative supply +0.5V to -95V OTP, Over Temperature Protection output -0.5V to +7.0V All logic input PIN X, NINX and EN voltages -0.5V to +7.0V (VSUB - VPP) Substrate to VPP voltage difference +190V (VPP - TXPX) VPP to TXPX voltage difference +190V (VSUB - TXPX) Substrate to TXPX voltage difference +190V (TXNX - VNN ) TXNX to VNN voltage difference +190V Operating temperature -40°C to +125°C Storage temperature -65°C to +150°C Thermal resistance, θ JA, (4 layer, 1oz., 4x3”, 36-via PCB) 12.8°C/W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Power-Up Sequence 1V SUB 2V LL with logic signal low 3V DD 4( V PP - VPF) and (VNF - VNN) 5V PP and VNN

6 Logic control signals

1 All logic signals go to low

3( V PP - VPF) and (VNF - VNN) 4V DD 5V LL 6V SUB Pin Confi guration Package Marking A B C D E F G H 1 2 3 4 5 6 7 8 64-Ball FCBGA (top view) YY = Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging YYWW HV758FB LLLLLLLLL 64-Ball FCBGA -G indicates package is RoHS compliant (‘Green’)

Operating Supply Voltages and Current (4 Channel Active) (Operating conditions, unless otherwise specifi ed, VSS = 0V, VLL = +3.3V, VDD = +10V, VPP-VPF = +10V, VNN-VNF = -10V, VPP =+90V, VNN = -90V, TA = 25°C) Symbol Parameter Min Typ Max Units Conditions VLL Logic voltage reference 1.2 2.5 5.0 V --- VDD Internal voltage supply 7.5 12 12.6 V --- VPF Positive gate driver supply (V PP-12.6) (V PP-12) (V PP-7.5) V Floating driver voltage supplies equals VDD.VNF Negative gate drive supply (V NN+7.5) (V NN+12) (V NN+12.6) V VSUB IC substrate voltage V DD VPP +90 V Must be the most positive potential of the IC. VPP Positive HV supply 0 - +90 V --- VNN Negative HV supply -90 - 0 V --- SRmax Allowable slew rate on VPP, VNN - - 25 V/μs --- ILL VLL Current EN = Low - 125 250 μA --- IDDQ VDD Current EN = Low - 100 - μA --- IDDEN VDD Current EN = High - 1.1 2.0 mA f = 0MHz IDDEN VDD Current MODE = 4 - 3.2 - mA f = 5.0MHz, continuous, no loadsIDDENCW VDD Current MODE = 1 - 3.1 - mA IPPQ VPP Current EN = Low - 74 90 μA f = 0MHz IPPEN VPP Current MODE = 4 - 258 - mA f = 5.0MHz, continuous, no loadsIPPENCW VPP Current MODE = 1 - 215 - mA INNQ VNN Current EN = Low - 78 90 μA f = 0MHz INNEN VNN Current MODE = 4 - 258 - mA f = 5.0MHz, continuous, no loadsINNENCW VNN Current MODE = 1 - 215 - mA IPFQ VPF Current EN = Low - 37 70 μA f = 0MHz IPFEN VPF Current MODE = 4 - 70 - mA f = 5.0MHz, continuous, no loadsIPFENCW VPF Current MODE = 1 - 9.0 - mA INFQ VNF Current EN = Low - 35 70 μA f = 0MHz INFEN VNF Current MODE = 4 - 42 - mA f = 5.0MHz, continuous, no loadsINFENCW VNF Current MODE = 1 - 6.0 - mA Note: All supply current values are for reference only. Under Voltage and Over Temperature Protection Symbol Parameter Min Typ Max Units Conditions VPULL_UP Open drain pull-up voltage - - 5.0 V --- VUVDD VDD threshold 3.5 5.7 7.0 V --- VUVLL VLL threshold 0.8 0.9 1.0 V --- VUVVF VPF, VNF threshold 2.7 4.0 5.4 V --- VOL_OTP OTP fl ag output low voltage - - 1.0 V VLL = 2.5V, OTP = Active, IPULL_UP = 1.0mA. IOTP Max. open drain output current - 1.0 - mA --- TOTP Over-temperature threshold 95 110 125 °C If over-temperature occurred, OTP low and all TX outputs will be HiZ.THYS OTP output reset hysteresis - 7.0 -

Electrical Characteristics

(Operating conditions, unless otherwise specifi ed, VSS = 0V, VLL = +3.3V, VDD = +10V, VPP-VPF = +10V, VNN-VNF = -10V, VPP =+90V, VNN = -90V, TA = 25°C) Output P-Channel MOSFET, TXP (Mode 4) Symbol Parameter Min Typ Max Units Conditions IOUT Output saturation current 2.2 2.5 - A --- RON Channel resistance - 11 - Ω I SD = 100mA COSS Output capacitance - 215 - pF V DS = 25V, f = 1.0MHz Output N-Channel MOSFET, TXN (Mode 4) Symbol Parameter Min Typ Max Units Conditions IOUT Output saturation current 2.1 2.2 - A --- RON Channel resistance - 11 - Ω I SD = 100mA COSS Output capacitance - 90 - pF V DS = 25V, f = 1.0MHz MOSFET Drain Bleed Resistor Symbol Parameter Min Typ Max Units Conditions RP/N1~4 Output bleed resistance 10 15 20 kΩ --- PRO Bleed resistors power limit - - 40 mW --- Logic Inputs Symbol Parameter Min Typ Max Units Conditions VIH Input logic high voltage (V LL-0.4) - V LL V --- VIL Input logic low voltage 0 - 0.4 V --- IIH Input logic high current - - 10 μA --- IIL Input logic low current -10 - - μA --- CIN Input logic capacitance - - 5.0 pF --- (Operating conditions, unless otherwise specifi ed, VSS = 0V, VLL = +3.3V, VDD = +10V, VPP-VPF = +10V, VNN-VNF = -10V, VPP =+90V, VNN = -90V, TA = 25°C) Symbol Parameter Min Typ Max Units Conditions tr Output rise time - 32 - ns 330pF//2.5kΩ loadtf Output fall time - 32 - ns fOUT Output frequency range 20 - - MHz 100Ω resistor load HD2 Second harmonic distortion - 30 - dB tEN Enable time - 70 250 μs tdr Delay time on inputs rise - 18 - ns tdf Delay time on inputs fall - 18 - ns tdm Delay on mode change - 2.5 20 μs ΔtDELAY Itdr-tdfI delay time matching - - ±3.0 ns P to N, channel to channel tj Delay jitter on rise or fall - 15 - ps VPP/VNN = +/-25V, input tr 50% to HVOUT tr or tf 50%, with 330pF//2.5kΩ load

Truth Table (All Modes) Logic Inputs Output EN PIN X NINX TXPX TXNX

100 O F F O F F

101 O F F O N

111 O N * O N *

0 X X OFF OFF

*Note: Not allowed, may damage IC tdr 50% 10% 50% 90% PINx NINx tdf Output VNN VPP tr 10% tf 90% Drive Mode Control Table Mode MC1 MC0 ISC (A) RONP (Ω) RONR (Ω) 1 0 0 0.58 28 27 2 0 1 0.8 20 19.7 3 1 0 1.35 12 11.7 4 1 1 2.5 6.5 6.3 Notes: 1.VPP/VNN = +/-90V, VDD = (VPP - VPF) = (VNF - VNN) = +10V 2. ISC is current into 1.0Ω to GND 3. RON calculated from VOUT into 100Ω load

VDD Positive internal voltage supply (+10V). VSS Power supply return (0V). VLL Logic Hi voltage reference input (+3.3V). GREF Logic Low reference, logic ground (0V). VSUB Substrate of the IC, all VSUB pins must connect externally to the most positive potential of the IC. RGND Bleed resistors common return ground. VPP Positive high voltage power supply (+90V). VNN Negative high voltage power supply (-90V). VPF P-FET drive fl oating power supply, (VPP - VPF) = +10V. VNF N-FET drive fl oating power supply, (VNF - VNN) = +10V. TXP1 Output P-FET drain (open drain output) for channel 1. TXN1 Output N-FET drain (open drain output) for channel 1. TXP2 Output P-FET drain (open drain output) for channel 2. TXN2 Output N-FET drain (open drain output) for channel 2. TXP3 Output P-FET drain (open drain output) for channel 3. TXN3 Output N-FET drain (open drain output) for channel 3. TXP4 Output P-FET drain (open drain output) for channel 4. TXN4 Output N-FET drain (open drain output) for channel 4. PIN1 Input logic control of high voltage output P-FET of channel 1, Hi=on, Low=off. NIN1 Input logic control of high voltage output N-FET of channel 1, Hi=on, Low=off. PIN2 Input logic control of high voltage output P-FET of channel 2, Hi=on, Low=off. NIN2 Input logic control of high voltage output N-FET of channel 2, Hi=on, Low=off. PIN3 Input logic control of high voltage output P-FET of channel 3, Hi=on, Low=off. NIN3 Input logic control of high voltage output N-FET of channel 3, Hi=on, Low=off. PIN4 Input logic control of high voltage output P-FET of channel 4, Hi=on, Low=off. NIN4 Input logic control of high voltage output N-FET of channel 4, Hi=on, Low=off. EN Chip power enable Hi=on, Low=off. MC0, MC1 Output current mode control pins, see Drive Mode Control Table. OTP Over temperature protection output, open N-FET drain, active low if IC temperature >110°C. Ball Description A 1 C o r n e r 12345678 AV PF VPP VPP VNN VNN VNF TXN4 TXN4 BV PF VPP VPP VNN VNN VNF TXP4 TXP4 CV DD VSUB PIN4 NIN4 MC0 V SUB TXN3 TXN3 DV SS OTP PIN3 NIN3 MC1 RGND TXP3 TXP3 EV SS VLL PIN2 NIN2 EN RGND TXN2 TXN2 FV DD VSUB PIN1 NIN1 G REF VSUB TXP2 TXP2 GV PF VPP VPP VNN VNN VNF TXN1 TXN1 HV PF VPP VPP VNN VNN VNF TXP1 TXP1 Ball Confi guration

(The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV758 NR061807 64-Ball FCBGA Package Outline (FB) 8x8mm body, 2.45mm height (max.), 0.80mm pitch A B C D E F G H 8 7 6 5 4 3 2 1 Note 1 (Index Area D/4 x E/4) Seating Plane E D e e SE SD A Detail A Top View Side View Bottom View Detail A Φb Symbol A A1 A2 ΦbDD 1E E 1 eS D S E Dimension (mm) 5.60 BSC 7.85 5.60 BSC 0.80 BSC 0.40 BSC 0.40 Drawings are not to scale. Note 1: Ball A1 identifi er must be located in the index area indicated. Ball A1 corner identifi cation can be used by ink or by metalized markings, or other features on package body. Shape of identifi er is optional.