HV746

HV746 SUTEX | Alldatasheet

Document overview

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Technical content

Features

HVCMOS technology for high performance High density integration ultrasound transmitter 0 to ±75V output voltage ±2.5A source and sink current in PW mode ±800mA source and sink current in CW mode Up to 20MHz operation frequency Matched delay times 1.2V to 5.0V CMOS logic interface Over temperature sensing Under voltage protections Built-in output drain bleed resistors

Applications

Portable medical ultrasound imaging Piezoelectric transducer drivers NDT ultrasound equipment Pulse waveform generator General Description The Supertex HV746 is a dual-channel monolithic high voltage high-speed pulse generator. It is designed for portable medical ultrasound applications. This high voltage and high-speed integrated circuit can also be used for other piezoelectric, capacitive or MEMS sensor in ultrasonic nondestructive detection and sonar ranger applications. The HV746 consists of controller logic interface circuit, level translators, MOSFET gate drives and high current power P- channel and N-channel MOSFETs as the output stage for each channel. A 2-bit mode control is provided that allows the maximum output current to be reduced for power saving. The output stages of each channel are designed to provide peak output currents over ±3.6A for pulsing, when in mode 4, with up to ±75V swings. When in mode 1, all the output stages drop the peak current to ±800mA for low-voltage CW mode operation to save power consumption of the IC. The P and N type of power FETs gate drivers are supplied by two fl oating 9.0VDC power supplies reference to V PP and VNN. This direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the PCB layout easier. Typical Application Circuit Dual High Speed ±75V 2.5A Ultrasound Pulser NIN1 SU B VPP -9V VPFVDD +9V GREF +1.8 to 3.3V Logic VPP 0 to +75V EN MC1 VNN 0 to -75V TXN1 VNN +9V 1 of 2 Channels C2 C3 C5C4 TXP1 HVOUT1 VNF VSUBVLL +1.8 to 3.3V +75V EN_P WR MC0 OTP VSS PIN1 RP1 RN1 RGND HV746 Level Translator RGND P-Driver N-Driver Level Translator

Ordering Information

7x7mm body, 1.0mm height (max), 0.5mm pitch HV746 HV746K6-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value VSS, Power supply reference 0V VLL, Positive logic supply -0.5V to +7V VDD, Positive logic and level translator supply -0.5V to +14V (VPP -VPF) Positive fl oating gate drive supply -0.5V to +14V (VNF- VNN) Negative gate fl oating drive supply -0.5V to +14V (VPP-VNN) Differential high voltage supply +180V VPP, High voltage positive supply -0.5V to +95V VNN, High voltage negative supply +0.5V to -95V All logic input PIN, NIN and EN pin voltages -0.5V to +7.0V OTP, over temperature protection output -0.5V to +7.0V SUB - VSS) Substrate to VSS voltage difference +180V (VPP –TXPX) VPP to TXPX voltage difference +180V (VSUB- TXPX) Substrate to TXPX voltage difference +180V (TXNX-VNN ) TXNX to VNN voltage difference +180V dVPP/dt, HV positive supply maximum slew rate 25V/μs dVNN/dt, HV negative supply maximum slew rate 25V/μs Storage temperature -65°C to 150°C Thermal resistance, θ JA (4-layer,1oz, 4x3in. 9-via PCB) 29°C/W Thermal resistance, θJC 0.5°C/W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Power-Up Sequence 1V SUB 2V LL with logic signal low 3V DD 4( V PP –VPF) and (VNF–VNN) 5V PP and VNN

6 Logic control signals go to hi

1 Logic control signals go to low

3( V PP –VPF) and (VNF–VNN) 4V DD 5V LL 6V SUB Pin Confi guration Package Marking 48-Lead QFN (K6) 48-Lead QFN (K6) (Top View) L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging HV746K6 LLLLLLLLL YYWW AAA CCC

Operating Supply Voltages and Current (2 Channel Active) (Operating conditions, unless otherwise specifi ed, VSS= 0V, VLL= +3.3V, VDD= +9.0V, VPP-VPF= +9.0V, VNN- VNF= -9.0V, VPP= +75V, VNN= -75V,TA= 25°C) Sym Parameter Min Typ Max Units Conditions VLL Logic voltage reference 1.2 1.8 to 3.3 5.0 V --- VDD Internal voltage supply 8.0 9.0 12 V --- VPF P-FET gate driver supply (V PP-12) (V PP-9.0) (V PP-8.0) V Floating driver voltage supplies.VNF N-FET gate drive supply (V NN+8.0) (V NN+9.0) (V NN+12) V VSUB IC substrate voltage V DD VPP +75 V Must connect to the most positive potential of the IC. VPP Positive HV supply 0 - +75 V --- VNN Negative HV supply -75 - 0 V --- SRMAX Slew rate limit of VPP, VNN - - 25 V/ms Built-in slew rate detection protection. ILL VLL Current EN = Low - 35 120 μA --- IDDQ VDD Current EN = Low - 15 - μA --- IDDEN VDD Current EN = High - 0.75 2.0 mA f = 0MHz IDDEN VDD Current MODE = 4 - 0.75 - mA f = 5.0MHz, continuous, no loadsIDDENCW VDD Current MODE = 1 - 2.0 - IPPQ VPP Current EN = Low - 10 25 μA --- IPPEN VPP Current MODE = 4 - 250 - mA f = 5.0MHz, continuous, no loadsIPPENCW VPP Current MODE = 1 - 170 - INNQ VNN Current EN = Low - 15 30 μA --- INNEN VNN Current MODE = 4 - 250 - mA f = 5.0MHz, continuous, no loadsINNENCW VNN Current MODE = 1 - 170 - IPFQ VPF Current EN = Low - 10 25 μA --- IPFEN VPF Current MODE = 4 - 50 - mA f = 5.0MHz, continuous, no loadsIPFENCW VPF Current MODE = 1 - 12 - INFQ VNF Current EN = Low - 20 30 μA --- INFEN VNF Current MODE = 4 - 25 - mA f = 5.0MHz, continuous, no loadsINFENCW VNF Current MODE = 1 - 12 - Under Voltage and Over Temperature Protection Sym Parameter Min Typ Max Units Conditions VPULL_UP Open drain pull-up voltage - - 5.0 V --- VUVDD VDD threshold 4.5 - 6.0 V --- VUVLL VLL threshold 0.8 0.9 1.0 V --- VUVVF VPF, VNF threshold 4.5 - 6.0 V --- VOL_OTP OTP fl ag output low voltage - - 1.0 V VLL= 3.3V, OTP = Active, IPULL-UP= 1.0mA IOTP Max. open drain output current - 1.0 - mA VLL= 3.3V, OTP = Active, IPULL-UP= 1.0mA TOTP Over temperature threshold 95 110 125 °C If over temperature occurs, OTP low and all TX outputs will be HiZ.T HYS OTP output reset hysteresis - 7.0 - °C

(Operating conditions, unless otherwise specifi ed, VSS= 0V, VLL= +3.3V, VDD= +9.0V, VPP-VPF= +9.0V, VNN- VNF= -9.0V, VPP= +75V, VNN= -75V,TA= 25°C) Output P-Channel MOSFET, TXP (Mode 4) Sym Parameter Min Typ Max Units Conditions IOUT Output saturation current 2.5 3.6 - A --- RON Channel resistance - 4.0 - Ω I SD = 100mA COSS Output capacitance - 200 - pF V DS = 25V, f = 1.0MHz Output N-Channel MOSFET, TXN (Mode 4) Sym Parameter Min Typ Max Units Conditions IOUT Output saturation current 2.5 3.6 - A --- RON Channel resistance - 3.75 - Ω I SD = 100mA COSS Output capacitance - 80 - pF V DS = 25V, f = 1.0MHz MOSFET Drain Bleed Resistor Sym Parameter Min Typ Max Units Conditions RP/N1~4 Output bleed resistance 5.0 7.5 10 kΩ --- PRO Bleed resistors power limit - - 80 mW --- Logic Inputs Sym Parameter Min Typ Max Units Conditions VIH Input logic high voltage (V LL- 0.4) - V LL V --- VIL Input logic low voltage 0 - 0.4 V --- IIH Input logic high current - - 10 μA --- IIL Input logic low current -10 - - μA --- CIN Input logic capacitance - - 10 pF --- (Operating conditions, unless otherwise specifi ed, VSS= 0V, VLL= +3.3V, VDD= +9.0V, VPP-VPF= +9.0V, VNN- VNF= -9.0V, VPP= +75V, VNN= -75V,TA= 25°C) Sym Parameter Min Typ Max Units Conditions tr Output rise time - 18 - ns 330pF//2.5kΩ loadtf Output fall time - 18 - ns fOUT Output frequency range - - 20 MHz 100Ω resistor load HD2 Second harmonic distortion - -28 - dB tEN Enable time - 180 500 μs tDIS Disable time - 2.8 10 μs tdr Delay time on inputs rise - 22 - ns tdf Delay time on inputs fall - 22 - ns tdm Delay on mode change - 2.5 10 ns Δtdelay |tdr - tdf| delay time matching - ±2.0 - ns tJ Delay jitter on rise or fall - 15 - ns VPP/VNN= +/-25V, input tr 50% to HVOUT tr or tf 50%, with 330pF//2.5kΩ load

(A) RON P (Ω) RON N (Ω) 1 0 0 0.82 18 17 2 0 1 1.16 13 12 3 1 0 1.94 7.5 7.0 4 1 1 3.6 4.0 3.8 Note: 1. VPP/VNN= +/-75V, VDD= (VPP –VPF) = (VNF–VNN) = +9.0V 2. ISC is current into 1.0Ω to GND 3. Ron calculated from VOUT into 100Ω load Switching Time Diagram tdr 50% 10% 50% 90% PINx NINx tdf Output VNN VPP tr 10% tf 90% Truth Table (Mode = X) Logic Inputs Output EN PIN X NINX TXPX TXNX

100 O F F O F F

1 1 1 ON* ON*

0 XX O F F O F F

Note: * Not allowed, may damage IC.

Pin # Name Function 1 VDD Positive internal voltage supply (+9.0V). 2 VSS Power supply return (0V). 3 PIN1 Input logic control of high voltage output P-FET of channel 1, Hi = ON, Low = OFF. 4 NIN1 Input logic control of high voltage output N-FET of channel 1, Hi = ON, Low = OFF. 5, 6, 7, 8 N/C Not Connected 9 PIN2 Input logic control of high voltage output P-FET of channel 2, Hi = ON, Low = OFF. 10 NIN2 Input logic control of high voltage output N-FET of channel 2, Hi = ON, Low = OFF. 11 VSS Power supply return (0V). 12 VDD Positive internal voltage supply (+9.0V). 13 OTP Over temperature protection output, open N-FET drain, active low if IC temperature >110°C.

14 MC1

Output current mode control pins, see Drive Mode Control Table.

15 MC0

16 VSUB Substrate of the IC, All VSUB pins must connect to the most positive potential of the IC externally.

17 VPF P-FET gate driver fl oating power supply, (V

PP- VPF) = +9.0V. 18,19, 20 VPP Positive high voltage power supply (+75V). 21, 22, 23 VNN Negative high voltage power supply (-75V). 24 VNF N-FET gate driver fl oating power supply, (V NF- VNN) = +9.0V. 25 VSUB Substrate of the IC, all VSUB pins must connect to the most positive potential of the IC externally. 26 RGND Bleed resistors common return ground. TXN2 Output N-FET drain (open drain output) for channel 2. TXP2 Output P-FET drain (open drain output) for channel 2. TXN1 Output N-FET drain (open drain output) for channel 1. TXP1 Output P-FET drain (open drain output) for channel 1. 35 RGND Bleed resistors common return ground. 36 VSUB Substrate of the IC, all VSUB pins must connect to the most positive potential of the IC externally.

37 VNF N-FET gate driver fl oating power supply, (V

NF- VNN) = +9.0V. 38, 39, 40 VNN Negative high voltage power supply (-75V). 41, 42, 43 VPP Positive high voltage power supply (+75V).

44 VPF P-FET gate driver fl oating power supply, (V

PP- VPF) = +9.0V. 45 VSUB Substrate of the IC, all VSUB pins must connect to the most positive potential of the IC externally. 46 EN Chip power enable Hi = ON, Low = OFF. 47 GREF Logic low reference, logic ground (0V). 48 VLL Logic Hi voltage reference input (+3.3V). Thermal Pad (VSUB) Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be connected to VSUB, the most positive potential of the IC externally.

(The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV746 A092707 48-Lead QFN Package Outline (K6) 7x7mm body, 1.0mm height (max), 0.50mm pitch Symbol A A1 A3 b D D2 E E2 e L L1 θ Dimension (mm) MIN 0.80 0.00 0.20 REF 0.50 BSC 0.30 0.00 0 O JEDEC Registration MO-220, Variation VKKD-2, Issue K, June 2006. Drawings are not to scale. Notes: Details of Pin 1 identifi er are optional, but must be located within the indicated area. The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. The inner tip of the lead may be either rounded or square. Seating Plane Top View Side View Bottom View A D E b L View B View B Note 3 Note 2 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) e θ