HV738

HV738 SUTEX | Alldatasheet

Document overview

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Technical content

Features

HVCMOS technology for high performance High density integration ultrasound transmitter 0 to ±65V output voltage ±750mA source and sink current in Pulse mode ±110mA source and sink current in CW mode Up to 20MHz operating frequency Matched delay times 1.2V to 5.0V CMOS logic interface Built-in output drain bleed resistors Application Portable medical ultrasound imaging Piezoelectric transducer drivers NDT ultrasound transmission Pulse waveform generator General Description The Supertex HV738 is a four-channel, monolithic, high voltage, high speed pulse generator. It is designed for portable medical ultrasound applications. This high voltage and high speed integrated circuit can also be used for piezoelectric, capacitive or MEMS sensing in ultrasonic nondestructive detection and sonar ranger applications. The HV738 consists of a controller logic interface circuit, level translators, MOSFET gate drivers and high current power P-channel and N-channel MOSFETs as the output stage for each channel. The output stages of each channel are designed to provide peak output currents over ±1.1A for pulsing, when in mode 4, with up to ±65 volt swings. When in mode 1, all the output stages drop the peak current to ±140mA for low-voltage CW mode operation to decrease the power consumption of the IC. The P and N type of power FETs gate drivers are supplied by two fl oating 8.0VDC power supplies referenced to V PP and VNN. This direct coupling topology of the gate drivers not only eliminates two high voltage capacitors per channel, but also makes the PCB layout easier. Typical Application Circuit Quad High Speed ±65V 750mA Ultrasound Pulser NIN1 SUB +8V +1.5 to 2.5V Logic 0 to +65V EN MC1 0 to -65V TXN1 1 of 4 Channels C2 C3 C5C4 TXP1 +1.5 to 2.5V +65V C6C7 EN_PWR MC0 OTP PIN1 RGND RGND HV738 P-Driver N-Driver Level Translator Level Translator VPP - 8V VPFVDD GREF VPP VNN VNN + 8V HVOUT1 VNF VSUBVLL VSS RP1 RN1

Ordering Information

7x7mm body, 1.0mm height (max), 0.5mm pitch HV738 HV738K6-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value VSS, Power supply reference 0V VLL, Positive logic supply -0.5V to +7V VDD, Positive logic and level translator supply -0.5V to +14V (VPP -VPF) Positive fl oating gate drive supply -0.5V to +14V (VNF- VNN) Negative gate fl oating drive supply -0.5V to +14V (VPP-VNN) Differential high voltage supply +140V VPP, High voltage positive supply -0.5V to +70V VNN, High voltage negative supply +0.5V to –70V OTP, Over Temperature Protection output -0.5V to +7V All logic input PIN X, NINX and EN voltages -0.5V to +7V (VSUB - VSS) Substrate to VSS voltage difference +140V (VPP –TXPX) VPP to TXPX voltage difference +140V (VSUB- TXPX) Substrate to TXPX voltage difference +140V (TXNX-VNN ) TXNX to VNN voltage difference +140V Operating temperature -40°C to 125°C Storage temperature -65°C to 150°C Thermal resistance, θ JA 29°C/W Thermal resistance, θJC (Junction to thermal pad) 0.5°C/W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Power-Up Sequence 1V SUB 2V LL with logic signal low 3V DD 4( V PP -VPF) and (VNF –VNN) 5V PP and VNN

6 Logic control signals

1 All logic signals go to low

3( V PP -VPF) and (VNF –VNN) 4V DD 5V LL 6V SUB Pin Confi guration Package Marking 48-Lead QFN (K6) (Top View) L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging HV738K6 LLLLLLLLL YYWW AAA CCC 48-Lead QFN

Operating Supply Voltages and Current (4 Channel Active) (Operating conditions, unless otherwise specifi ed, VSS = 0V, VLL = +2.5V, VDD = +8V, VPP-VPF = +8V, VNN-VNF = -8V, VPP =+65V, VNN = -65V, TA = 25°C) Symbol Parameter Min Typ Max Units Conditions VLL Logic voltage reference 1.2 2.5 5.0 V --- VDD Internal voltage supply 7.5 8.0 10 V --- VSUB IC substrate voltage V DD VPP +65 V Must be the most positive potential of the IC. VPP Positive HV supply 0 - +65 V --- VNN Negative HV supply -65 - 0 V --- SRMAX Slew rate limit of VPP, VNN - - 25 V/μs Built-in slew rate detection protection. ILL VLL Current EN = Low - 35 120 μA --- IDDQ VDD Current EN = Low - 10 - μA --- IDDEN VDD Current EN = High - 0.75 2.0 mA f = 0MHz IDDEN VDD Current MODE = 4 - 2.0 - mA f = 5.0MHz, continuous, no loadsIDDENCW VDD Current MODE = 1 - 5.0 - mA IPPQ VPP Current EN = Low - 10 20 μA f = 0MHz IPPEN VPP Current MODE = 4 - 200 - mA f = 5.0MHz, continuous, no loadsIPPENCW VPP Current MODE = 1 - 140 - mA INNQ VNN Current EN = Low - 10 20 μA f = 0MHz INNEN VNN Current MODE = 4 - 170 - mA f = 5.0MHz, continuous, no loadsINNENCW VNN Current MODE = 1 - 140 - mA IPFQ VPF Current EN = Low - 8.0 20 μA f = 0MHz IPFEN VPF Current MODE = 4 - 30 - mA f = 5.0MHz, continuous, no loadsIPFENCW VPF Current MODE = 1 - 10 - mA INFQ VNF Current EN = Low - 10 20 μA f = 0MHz INFEN VNF Current MODE = 4 - 12 - mA f = 5.0MHz, continuous, no loadsINFENCW VNF Current MODE = 1 - 5.0 - mA Under Voltage and Over Temperature Protection Symbol Parameter Min Typ Max Units Conditions VPULL_UP Open drain pull-up voltage - - 5.0 V --- VUVDD VDD threshold 3.5 6.0 7.0 V --- VUVLL VLL threshold 0.8 0.9 1.0 V --- VUVVF VPF, VNF threshold 2.7 4.75 5.4 V --- VOL_OTP OTP fl ag output low voltage - - 1.0 V VLL = 2.5V, OTP = Active, IPULL_UP = 1.0mA. IOTP Max. open drain output current - 1.0 - mA --- TOTP Over-temperature threshold 95 110 125 °C If over-temperature occurred, OTP low and all TX outputs will be HiZ.THYS OTP output reset hysteresis - 7.0 -

Electrical Characteristics

(Operating conditions, unless otherwise specifi ed, VSS = 0V, VLL= +2.5V, VDD = +8V, VPP-VPF = +8V, VNN-VNF = -8V, VPP = +65V, VNN = -65V,TA = 25°C) Output P-Channel MOSFET, TXP (Mode 4) Symbol Parameter Min Typ Max Units Conditions IOUT Output saturation current 0.75 1.2 - A --- RON Channel resistance - 13 - Ω I SD = 100mA COSS Output capacitance - 50 - pF V DS = 25V, f = 1.0MHz Output N-Channel MOSFET, TXN (Mode 4) Symbol Parameter Min Typ Max Units Conditions IOUT Output saturation current 0.75 1.1 - A --- RON Channel resistance - 12.5 - Ω I SD = 100mA COSS Output capacitance - 20 - pF V DS = 25V, f = 1.0MHz MOSFET Drain Bleed Resistor Symbol Parameter Min Typ Max Units Conditions RP/N1~4 Output bleed resistance 10 15 20 kΩ --- PRO Bleed resistors power limit - - 40 mW --- Logic Inputs Symbol Parameter Min Typ Max Units Conditions VIH Input logic high voltage (V LL-0.4) - V LL V --- VIL Input logic low voltage 0 - 0.4 V --- IIH Input logic high current - - 10 μA --- IIL Input logic low current -10 - - μA --- CIN Input logic capacitance - - 5.0 pF --- (Operating conditions, unless otherwise specifi ed, VSS = 0V, VLL = +2.5V, VDD = +8V, VPP - VPF = +8V, VNN - VNF= -8V, VPP = +65V, VNN = -65V,TA= 25°C) Symbol Parameter Min Typ Max Units Conditions tr Output rise time - 35 - ns 330pF//2.5kΩ loadtf Output fall time - 43 - ns fOUT Output frequency range - - 20 MHz 100Ω resistor load HD2 Second harmonic distortion - -35 - dB tEN Enable time - 180 500 μs tDIS Disable time - 2.8 10 μs tdr Delay time on inputs rise - 22 - ns tdf Delay time on inputs fall - 22 - ns tdm Delay on mode change - 2.5 10 μs ΔtDELAY |tdr - tdf| Delay time matching - - ±3.0 ns P to N, channel to channel tj Delay jitter on rise or fall - 13 - ps VPP/VNN = ±25V, input tr 50% to HVOUT tr or tf 50%, with 330pF//2.5kΩ load

Truth Table (All Modes) Logic Inputs Output EN PIN X NINX TXPX TXNX

100 O F F O F F

101 O F F O N

111 O N * O N *

0 X X OFF OFF

*Note: Not allowed, may damage IC tdr 50% 10% 50% 90% PINx NINx tdf Output VNN VPP tr 10% tf 90% Drive Mode Control Table Mode MC1 MC0 ISC (A) RONP (Ω) RONR (Ω) 1 0 0 0.28 56.0 54.0 2 0 1 0.38 41.0 39.5 3 1 0 0.65 24.0 23.0 4 1 1 1.20 13.0 12.5 *Note: 1.VPP/VNN = +/-65V, VDD = (VPP – VPF) = (VNF – VNN) = +8.0V 2. ISC is current into 1.0Ω to GND 3. RON calculated from VOUT into 100Ω load

Pin # Name Function 1, 12 V DD Positive internal voltage supply (+8.0V). 2, 11 V SS Power supply return (0V). 48 V LL Logic Hi voltage reference input (+2.5V). 47 G REF Logic Low reference, logic ground (0V). 26, 35 RGND Bleed resistors common return ground. (Both pins must be used) 18, 19, 20, 41, 42, 43 VPP Positive high voltage power supply (+65V). 21, 22, 23, 38, 39, 40 VNN Negative high voltage power supply (-65V). 17, 44 V PF P-FET drive fl oating power supply, (VPP- VPF) = +8.0V. 24, 37 V NF N-FET drive fl oating power supply, (VNF- VNN) = +8.0V. 34 TXP1 Output P-FET drain (open drain output) for channel 1. 33 TXN1 Output N-FET drain (open drain output) for channel 1. 32 TXP2 Output P-FET drain (open drain output) for channel 2. 31 TXN2 Output N-FET drain (open drain output) for channel 2. 30 TXP3 Output P-FET drain (open drain output) for channel 3. 29 TXN3 Output N-FET drain (open drain output) for channel 3. 28 TXP4 Output P-FET drain (open drain output) for channel 4. 27 TXN4 Output N-FET drain (open drain output) for channel 4. 3 PIN1 Input logic control of high voltage output P-FET of channel 1, Hi=on, Low=off. 4 NIN1 Input logic control of high voltage output N-FET of channel 1, Hi=on, Low=off. 5 PIN2 Input logic control of high voltage output P-FET of channel 2, Hi=on, Low=off. 6 NIN2 Input logic control of high voltage output N-FET of channel 2, Hi=on, Low=off. 7 PIN3 Input logic control of high voltage output P-FET of channel 3, Hi=on, Low=off. 8 NIN3 Input logic control of high voltage output N-FET of channel 3, Hi=on, Low=off. 9 PIN4 Input logic control of high voltage output P-FET of channel 4, Hi=on, Low=off. 10 NIN4 Input logic control of high voltage output N-FET of channel 4, Hi=on, Low=off. 46 EN Chip power enable Hi=on, Low=off.

15 MC0

Output current mode control pins, see Drive Mode Control Table.

14 MC1

13 OTP Over temperature protection output, open N-FET drain,

active low if IC temperature >110°C. 16, 25, 36, Thermal Pad SUB) Substrate of the IC, Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be connected to V SUB, the most positive potential of the IC externally. Pin Description

(The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV738 NR060807 48-Lead QFN Package Outline (K6) 7x7mm body, 1.0mm height (max), 0.50mm pitch Symbol A A1 A3 b D D2 E E2 e L L1 θ Dimension (mm) MIN 0.80 0.00 0.20 REF 0.50 BSC 0.30 0.00 0 O JEDEC Registration MO-220, Variation VKKD-2, Issue K, June 2006. Drawings are not to scale. Notes: Details of Pin 1 identifi er are optional, but must be located within the indicated area. The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. The inner tip of the lead may be either rounded or square. Seating Plane Top View Side View Bottom View A D E b L View B View B Note 3 Note 2 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) e θ