HV7360

HV7360 SUTEX | Alldatasheet

Document overview

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Technical content

Features

► HVCMOS® technology for high performance ► High density integration AC coupled pulser ► 0 to ±100V output voltage ► ±2.5A source and sink minimum pulse current ► Up to 35MHz operating frequency ► 2.0ns matched delay times ► 2.5, 3.3 or 5.0V CMOS logic interface ► Low power consumption and very simple to use Application ► Medical ultrasound imaging ► Piezoelectric transducer drivers ► NDT ultrasound transmission ► Pulse waveform generator General Description The Supertex HV7360 is a high voltage, high-speed, pulse generator with built-in, fast return to zero damping FETs. This high voltage and high-speed integrated circuit is designed for portable medical ultrasound image devices, but can also can be used for NDT and test equipment applications. The HV7360 consists of a controller logic interface circuit, level translators, AC coupled MOSFET gate drivers and high voltage and high current P-channel and N-channel MOSFETs as the output stage. The peak output currents of each channel are guaranteed to be over ±2.5A with up to ±100V of pulse swing. The AC coupling topology for the gate drivers not only saves two floating voltage supplies, it also makes the PCB layout easier. Typical RTZ Application Circuit High Speed, ±100V 2.5A, Two or Three Level Ultrasound Pulser +2.5/3.3V VLL VDDV H INA INB PE VL1GND INC IND VSS SP1 SP2 SN1 SN2 DP1 DP2 VNN 0 to -100V +10V 2.5/3.3V Logic Input DN2 DN1 VL2 VL3 +10V HVOUT VPP 0 to +100V

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Pad Configuration Package Marking 22-Lead LFGA (LA) Package may or may not include the following marks: Si or 22-Lead LFGA (LA) (top view) Parameter Value VDD – VSS Logic supply voltage -0.5 to +12.5V VH Output high supply voltage VL -0.5 to VDD +0.5V VL Output low supply voltage VSS -0.5V to VH +0.5V VSS Low side supply voltage -6.0 to +0.5V (VSPx - VSNx) Differential high voltage +220V VSPx Positive high voltage -0.5 to +110V VSNx Negative high voltage +0.5 to -110V All logic input voltages VSS -0.5V to GND +5.5V Coupling capacitor breakdown voltage ±110V Maximum junction temperature 125°C Operating temperature -20 to +85°C PE Input Pulse Output MOSFETs INA INB INC IND SP1 to DP1 DN1 to SN1 SP2 to DP2 DN2 to SN2

1 X X X ON X X X

0 X X X OFF X X X

0 X X X X OFF OFF OFF OFF

A B C D E F G H J K L M N P -G indicates package is RoHS compliant (‘Green’)

Ordering Information

Part Number Package Option Packing HV7360LA-G 22-Lead LFGA 364/Tray Power-Up Sequence Step Description

1 VLL

2 VDD, VH, VSS, VL with signal logic low

3 VPP and VNN

4 PE active

1 PE inactive

2 VPP and VNN off

3 VDD, VH, VSS, VL off

4 VLL off

Note: Powering up/down in any arbitrary sequence will not cause any damage to the device. The powering up/down sequence is only recommended in order to minimize possible inrush current. HV7360 LLLLLL YYWW AAACCC L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging Typical Thermal Resistance Package θja 22-Lead LFGA 106OC/W

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Operating Supply Voltages and Current (Operating conditions, unless otherwise specified, GND = 0V, VH = VDD = +10V, VL = VSS = 0V, VPE = 3.3V, VPP = +100V, VNN = -100V, TA = 25°C) Sym Parameter Min Typ Max Unit Conditions VDD – VSS Supply voltage 4.75 - 11.50 V 4.0 ≤ VDD ≤ 11.5V VSS Low side supply voltage -5.5 - 0 V --- VH Output high supply voltage VSS +4.0 - VDD V VH - VL ≥ 4.0V VL Output low supply voltage VSS - VDD -4.0 V IDDQ VDD quiescent current - 50 - μA No input transitions, PE = 0IHQ VH quiescent current - 2.0 - μA IDDQ VDD quiescent current - 1.0 - mA No input transitions, PE = 1I HQ VH quiescent current - 2.0 - μA IDD VDD average current - 4.0 - mA One channel ON at 5.0Mhz, No loadI H VH average current - 10 - mA VIH Input logic voltage high VPE -0.3 - VPE V For logic inputs INA, INB, INC, and IND V IL Input logic voltage low 0 - 0.3 V IIH Input logic current high - - 1.0 μA IIL Input logic current low - - 1.0 μA VPEH PE input logic voltage high 1.70 3.30 5.25 V For logic input PEVPEL PE input logic voltage low 0 - 0.3 V RINPE PE input impedance to GND 100 - - kΩ (Operating conditions, unless otherwise specified, GND = 0V, VH = VDD = +10V, VL = VSS = 0V, VPE = 3.3V, VPP = +100V, VNN = -100V, TA = 25°C) Sym Parameter Min Typ Max Unit Conditions tirf Input or PE rise & fall time - - 10 ns Logic input edge speed requirement t d1-4 Input to output delay - 7.5 - ns RLOAD = 1.0Ω tr/f1-2 Output rise/fall time - 9.5 - ns CLOAD = 330pF, RLOAD = 2.5kΩ Δtrf Rise and fall time matching - 2.0 - ns Channel to channel ΔtdC2C Propagation matching - 1.0 - ΔtdD2D Propagation delay matching - ±2.0 - ns Device to device delay match t PE-ON PE ON-time - - 5.0 µs VPE = 1.7 ~ 5.25V VDD = 7.5 ~ 11.5V -20 ~ 85OCtPE –OFF PE OFF-time - - 4.0 COG Output to MOSFET gate cap - 10 - nF 100V X7S CVH VH to VL3 decoupling cap - 0.22 - µF 16V X7R

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Pulser & Damping P-Channel MOSFET Sym Parameter Min Typ Max Unit Conditions BVDSS Drain-to-source breakdown voltage -200 - - V VGS = 0V, ID = -2.0mA VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID = -1.0mA ΔVGS(th) Change in VGS(th) with temperature - - 4.5 mV/OC VGS = VDS, ID = -1.0mA RGS Gate-to-source shunt resistor 10 - 50 kΩ IGS = 100µA, if applied VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = -2.0mA, if applied IDSS Zero gate voltage drain current - - -10 μA VDS = max rating, VGS = 0V - - -1.0 mA VDS = 0.8max rating, VGS = 0V, TA = 125OC ID(ON) ON-state drain current -1.2 - - A VGS = -5.0V, VDS = -25V RDS(ON) Static drain-to-source ON-state resistance - - 8.5 Ω VGS = -5.0V, ID = -150mA ΔRDS(ON) Change in RDS(ON) with temperature - - 1.0 %/OC VGS = -10V, ID = -1.0mA GFS Forward transconductance 400 - - mmho VDS = -25V, ID = -500mA CISS Input capacitance - 75 - pF VGS = 0V, VDS = -25V, f = 1.0MHz COSS Common source output capacitance - 21 - CRSS Reverse transfer capacitance - 6.5 - VSBD Diode forward voltage drop and reverse recovery time of body-diode - - 1.8 V VGS = 0V, ISD = 500mA trrBD - 300 - ns --- Pulser & Damping N-Channel MOSFET Sym Parameter Min Typ Max Unit Conditions BVDSS Drain-to-source breakdown voltage 200 - - V VGS = 0V, ID = 2.0mA VGS(th) Gate threshold voltage 1.0 - 2.4 V VGS = VDS, ID = 1.0mA ΔVGS(th) Change in VGS(th) with temperature - - -4.5 mV/OC VGS = VDS, ID = 1.0mA RGS Gate-to-source shunt resistor 10 - 50 kΩ IGS = 100µA VZGS Gate-to-source Zener voltage 13.2 - 25 V IGS = 2.0mA IDSS Zero gate voltage drain current - - 10 μA VDS = max rating, VGS = 0V - - 1.0 mA VDS = 0.8max rating, VGS = 0V, TA = 125OC ID(ON) ON-state drain current 1.3 - - A VGS = 5.0V, VDS = 25V 2.3 2.5 - VGS = 10V, VDS = 50V RDS(ON) Static drain-to-source ON-state resistance - - 6.5 Ω VGS = 5.0V, ID = 150mA - - 6.0 VGS = 10V, ID = 1.0A ΔRDS(ON) Change in RDS(ON) with temperature - - 1.0 %/OC VGS = 10V, ID = 1.0A GFS Forward transconductance 400 - - mmho VDS = 25V, ID = 500mA CISS Input capacitance - 56 - pF VGS = 0V, VDS = 25V, f = 1.0MHz COSS Common source output capacitance - 13 - CRSS Reverse transfer capacitance - 2.0 - VSBD Diode forward voltage drop and reverse recovery time of body-diode - - 1.8 V V GS = 0V, ISD = 500mA trrBD - 300 - ns ---

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Switch Timing and Delay Test INA INB TX + DMP tf2 50%INA IOUT +2.5/3.3V VLL VDD VH INA INB PE VLGND INC IND VSS SP1 SP2 SN1 SN2 DP1 DP2 -100V +10V 2.5/3.3V Logic Input DN2 DN1 VL3 +10V +100V TX + DMPtr1 tr2tf1 td1 td3 td2 td4 50% 50% 50%90% 90% 10% 10% IOUT INB

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Typical Unipolar 2-Channel Application Circuit +2.5/3.3V VLL VDDV H INA INB PE VL1GND INC IND VSS SP1 SP2 SN1 SN2 DP1 DP2 VPP +10V 2.5/3.3V Logic Input DN2 DN1 VL2 VL3 +10V VPP = 0 to +100V TX2 TX1 Pad Description Pad Location Name Function A1 GND Driver and level translator circuit ground return (0V) A2 IND Damping N-FET control signal logic Input, controlling N-FET2 A3 INC Damping P-FET control signal logic Input, controlling P-FET2 A4 VSS Negative voltage power supply (0V) A6 VDD Positive voltage supply (+10V), should connect to an external decoupling cap to VSS (0V) A7 INB Pulsing N-FET control signal logic Input, controlling N-FET1 A8 INA Pulsing P-FET control signal logic Input, controlling P-FET1 A9 PE Drive power enable Hi = ON, Low = OFF , logic “1” voltage reference input (+1.8 to +3.3V) B2 VL2 Gate-Drive negative voltage power supply (0V) B8 VL1 Gate-Drive negative voltage power supply (0V) F4 VH Gate driver positive voltage power supply (+10V) F7 VL3 VH to VL decoupling cap, should connect to VL1 & VL2 (0V) ground plane as short as possible G4 NC Do not connect P1 SP2 Source of P-FET2, positive high voltage power supply (0 to +100V) or GND P2 DP2 Drain of P-FET2, transmit pulser output P3 DN2 Drain of N-FET2, transmit pulser output

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Pad Description (cont.) Pad Location Name Function P4 SN2 Source of N-FET2, negative high voltage power supply (0 to -100V) or GND P5 NC Do not connect P6 SP1 Source of P-FET1, positive high voltage power supply (0 to +100V) P7 DP1 Drain of P-FET1, transmit pulser output P8 DN1 Drain of N-FET1, transmit pulser output P9 SN1 Source of N-FET1, negative high voltage power supply (0 to -100V) Pad Configuration (Top View) A B C D E F G H J K L M N P 4.0mm 3.50mm2.00mm 0.50mm0.50mm 0.50mm 5.0mm 7.0mm

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com HV7360 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) 22-Lead LFGA Package Outline (LA) 5.00x7.00mm body, 0.85mm height (max), 0.50mm pitch Symbol A b D E e e1 e2 e3 Dimension (mm) MIN 0.75 0.20 4.925 6.925 0.50 BSC 2.00 BSC 3.50 BSC 4.00 BSCNOM 0.80 0.25 5.000 7.000 MAX 0.85 0.30 5.075 7.075 Drawings not to scale. Supertex Doc. #: DSPD-22LFGALA, Version A052511. D Top View Bottom View E Side View View A A b b View A e A B C D E F G H J K L M N P e e 9 8 7 6 5 4 3 2 1 Note 1 (Index Area D1/4 x E1/4) Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Doc.# DSFP-HV7360 A040512