HV7355 SUTEX | Alldatasheet
Document overview
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Technical content
Features
► HVCMOS technology for high performance ► High density integrated ultrasound transmitter ► 0 to +150V output voltage ► ±1.5A source and sink current (min.) ► ±300mA current in CW mode ► Up to 18MHz operating frequency ► Matched delay times ► Built-in gate driver floating voltage regulator ► 2.5 to 3.3V CMOS logic interface Application ► Portable medical ultrasound imaging ► Piezoelectric transducer drivers ► NDT ultrasound transmission ► Pulse waveform generator General Description The Supertex HV7355 is an eight-channel, unipolar, high voltage, high-speed pulse generator. It is designed for medical ultrasound applications. This high voltage and high speed integrated circuit can also be used for other piezoelectric, capacitive or MEMS sensors in ultrasonic nondestructive detection and sonar ranger applications. The HV7355 consists of a controller logic interface circuit, level translators, MOSFET gate drivers and high current P-channel and N-channel MOSFETs as the output stage for each channel. The output stages of each channel are designed to provide peak output currents over ±1.5A for pulsing, when MC = 1, with up to 150V swings. When MC = 0, all the output stages drop the peak current to ±500mA for low-voltage CW mode operation to save power. This direct coupling topology of the gate driver not only saves one high voltage capacitor per channel, but also makes the PCB layout easier. Typical Application Circuit Eight Channel, High Speed, Unipolar, Ultrasound Pulser 1.5A 150V LR TX0 LT IN0 IN7 VLL VDDVDD VPF VDDVDD VDD VPP GND MC TX7 VPP VPF VPP VSS VSS +5.0 to 150V+3.3V CPF VPPVDD LR VPF VDD +5.0V CWD Q[7:0] LT LT LT -5.0V SDI SDO SCK SET LE CS EN PWR RGND RGND RGND +3.3V Logic SUB AVDD VSUB Data Latch Shift Reg.
Supertex inc. www.supertex.com Doc.# DSFP-HV7355 D070813
Ordering Information
Part Number Package Options Packing HV7355K6-G 56-Lead QFN (8x8) 250/Tray HV7355K6-G M937 56-Lead QFN (8x8) 2000/Reel Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Power-Up Sequence Step Description
1 VSS
2 VLL with logic signal low
3 VDD
4 VPP
5 EN & logic signal go to high
1 EN & logic signal low
3 VPP
4 VDD
5 VLL
6 VSS
L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging HV7355K6 LLLLLLLLL YYWW AAA CCC 56-Lead QFN 56-Lead QFN (top view) Package may or may not include the following marks: Si or Parameter Value GND, RGND and VSUB 0V VLL, Positive logic supply -0.5V to +7.0V VDD, Positive logic and level translator supply -0.5V to +7.0V VSS, Negative level translator and LR supply +0.5V to -7.0V VPP, High voltage positive supply -0.5V to +160V ( VPP -VTXx) Voltage -0.5V to +160V (VTXx - RGND) Voltage -0.5V to +160V All logic input PINX, NINX and EN voltages -0.5V to +7.0V Operating temperature -40°C to 125°C Storage temperature -65°C to 150°C Note: Powering up/down in any arbitrary sequence will not cause any damage to the device. The powering up/down sequence is only recommended in order to minimize possible inrush current. Logic Inputs Output EN Q[7:0] IN0~7 TX0~7 1 1111,1111 0 GND 1 1111,1111 1 VPP 1 0 X GND
0 X X HiZ
Truth Table (MC = X) Drive Mode Control Table MC ISC (A) RonP RonN 0 0.50 18 13 1 1.6 8.0 3.0 Note: VPP = +150V, VDD = +5.0 V, VLL = +3.3V, VSS = -5.0V, VSUB = 0V Typical Thermal Resistance Package θja 56-Lead QFN (8.0x8.0 ) 21OC/W -G denotes a lead (Pb)-free / RoHS compliant package
Supertex inc. www.supertex.com Doc.# DSFP-HV7355 D070813 Operating Supply Voltages and Current (Eight Active Channels) (Operating conditions, unless otherwise specified, VLL = +3.3V, VADD = VDD = +5.0V, VSS = -5.0V ,VPP = +150V, TA = 25°C) Sym Parameter Min Typ Max Units Conditions VLL Logic voltage reference 2.37 3.30 3.47 V --- VDD Internal voltage supply 4.5 5.0 5.5 V --- VPP Positive gate driver supply VDD - +150 V --- VSS Negative low voltage supply -5.5 -5.0 -4.5 V --- VPF Gate driver floating voltage - 5.0 - V --- ILL VLL Current EN = Low - 2.0 10 μA --- IDDQ VDD Current EN = Low - 50 150 μA f = 0MHz IDDEN VDD Current EN = High - 1.0 4.0 mA f = 0MHz IDDEN VDD Current MC = High - 160 - mA f = 5.0MHz, continuous no loadsI DDENCW VDD Current MC = Low - 12 - mA ISSQ VSS Current EN = Low - 5.0 20 μA --- ISSEN VSS Current EN = High - 1.0 4.0 mA f = 0MHz ISSEN VSS Current MC = High - 95 - mA f = 5.0MHz, continuous no loadsI SSENCW VSS Current MC = Low - 50 - mA IPPQ VPP Current EN = Low - 2.0 10 μA --- IPPEN VPP Current EN = High - 200 450 μA f = 0MHz IPPEN VPP Current MC = High - 370 - mA f = 5.0MHz, continuous no loadsI PPENCW VPP Current MC = Low - 300 - mA Under Voltage and Over Temperature Protection Sym Parameter Min Typ Max Units Conditions VUVDD VDD threshold 3.4 - 4.4 V (Internal only) VUVLL VLL threshold - 1.7 - V (Internal only) VUVPF VPP - VPF threshold 2.5 - 3.8 V (Internal only) Logic Inputs (Operating conditions, unless otherwise specified, VLL = +3.3V, VADD = VDD = +5.0V, VSS = -5.0V ,VPP = +150V, TA = 25°C) Sym Parameter Min Typ Max Units Conditions VIH Input logic high voltage (VLL - 0.4) - VLL V --- VIL Input logic low voltage 0 - 0.4 V --- IIH Input logic high current - - 1.0 μA --- IIL Input logic low current -1.0 - - μA --- CIN Input logic capacitance - - 5.0 pF ---
Supertex inc. www.supertex.com Doc.# DSFP-HV7355 D070813
Electrical Characteristics
(Operating conditions, unless otherwise specified, VLL = +3.3V, VADD = VDD = +5.0V, VSS = -5.0V ,VPP = +150V, TA = 25°C) P-Channel MOSFET Output, TX0~7 Sym Parameter Min Typ Max Units Conditions IOUT Output saturation current 1.4 1.6 - A MC = 1 RON Channel resistance - 8.0 - Ω 100mA IOUT Output saturation current 0.5 - - A MC = 0 RON Channel resistance - 18 - Ω 100mA N-Channel MOSFET Output, TX0~7 Sym Parameter Min Typ Max Units Conditions IOUT Output saturation current 1.5 1.7 - A MC = 1 RON Channel resistance - 3.0 - Ω ISD = 100mA IOUT Output saturation current 0.5 - - A MC = 0 RON Channel resistance - 22 - Ω 100mA (Operating conditions, unless otherwise specified, VLL = +3.3V, VADD = VDD = +5.0V, VSS = -5.0V ,VPP = +150V, TA = 25°C) Sym Parameter Min Typ Max Units Conditions tinrf Input data rise/fall max time - - 10 ns --- tr Output rise time - 24 - ns 330pF//2.5kΩ load see timing test diagramt f Output fall time - 24 - ns fOUT Output frequency range - - 18 MHz 100Ω resistor load, VPP = +90V tEN-ON Initial enable time - 150 200 μs 2μF on each CPF pin to 90% of V CPF tEN-OFF Output disable time - 2.0 5.0 μs at 5.0MHz CW tdr Delay time on inputs rise - 5.0 - ns VPP = 25V 1.0Ω resistor load, 50% to 50% see timing test diagram t df Delay time on inputs fall - 5.0 - ns tdm Delay on mode change - 50 70 ns ΔtDELAY Delay time matching - ± 2.0 - ns P to N, channel to channel tj Delay jitter on rise or fall - 15 - ps --- Serial Data Interface Timing Characteristics (Operating conditions, unless otherwise specified, VLL = +3.3V, VADD = VDD = +5.0V, VSS = -5.0V ,VPP = +150V, TA = 25°C) Sym Parameter Min Typ Max Units Conditions fSCK Serial clock max. frequency 25 - - MHz All from/to 50% rise or fall edges (See timing diagram) t 1 SDI valid to SCK setup time 0 2.0 - ns t2 SDI valid to SCK hold time 4.0 - - ns t3 SCK high time 9.0 - - ns t4 SCK low time 9.0 - - ns t5 CS pulse width 9.0 - - ns t6 SCK high to CS high 7.0 - - ns t7 CS low to SCK high 7.0 - - ns t8 SDO delay from SCK rise edge - 6.5 - ns SDO with 100pF to GND t9 CS high to SCK rise edge 7.0 - - ns All from/to 50% rise or fall edges (See timing diagram)t 10 SCK high to LE low 7.0 - - ns
Supertex inc. www.supertex.com Doc.# DSFP-HV7355 D070813 Output Timing Test Diagram tdrx 50% INX tdfx IOUT TXX 50% tr tf 90% 10% TX0 LT IN0 IN7 VLL VDDVDD VPF VDDVDD VDD VPP GND MC TX7 VPP VPF VPP VSS VSS +5.0 to 150V+3.3V CPF VPPVDD LR VPF VDD +5.0V CWD Q[7:0] LT LT LT -5.0V SDI SDO SCK SET LE CS EN PWR RGND RGND RGND +3.3V Logic SUB AVDD VSUB Data Latch Shift Reg. Serial Data Interface Timing Diagram 12378SCK SDI CS SDO LE t3 t4 t5 t7 t10
Supertex inc. www.supertex.com Doc.# DSFP-HV7355 D070813 Pin Description Pin Name Description
1 IN0
Input control for channels 0~7
2 IN1
3 IN2
4 IN3
5 IN4
6 IN5
7 IN6
8 IN7
9 CS Serial interface enable, active low
10 SDI Serial shift register data input, MSB(D7) first, LSB(D0) last
11 LE Latch enable, active low
12 SCK Serial shift register clock
13 SDO Serial shift register data output
14 SET Set latch data Q[7:0] = 1, regardless the shift register inputs or LE, active high
15 MC Output current mode control pin, see Drive Mode Control Table
16 VLL Logic Hi voltage reference input (+3.3V) 17 VSS Negative power supply(-5.0V)
18 CPF Gate driver floating voltage decoupling capacitor to VPP
19 VPP
Positive high voltage power supply (+150V)
20 VPP
21 VPP
22 VPP
23 VDD Positive voltage supply for gate drivers (+5.0V)
24 RGND
Output return ground, 0V, RGND pins carry high current, must connect to load transducer ground
25 RGND
26 RGND
27 RGND
Supertex inc. www.supertex.com Doc.# DSFP-HV7355 D070813 Pin Description (cont.) Pin Name Description
28 TX7
Output for channel 0~7
29 TX7
30 TX6
31 TX6
32 TX5
33 TX5
34 TX4
35 TX4
36 TX3
37 TX3
38 TX2
39 TX2
40 TX1
41 TX1
42 TX0
43 TX0
44 RGND
Output return ground, 0V, RGND pins carry high current, must connect to load transducer ground
45 RGND
46 RGND
47 RGND
48 VDD Positive voltage supply for gate drivers (+5.0V)
49 VPP
Positive high voltage power supply (+150V)
50 VPP
51 VPP
52 VPP
53 CPF Gate driver floating voltage decoupling capacitor to V
54 GND Logic input reference ground, 0V
55 AVDD Positive internal voltage supply (+5.0V)
56 EN Chip power enable, active high
VSUB (Thermal Pad) Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be connected to GND (0V) externally
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888 www.supertex.com HV7355 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV7355 D070813 56-Lead QFN Package Outline (K6) 8.00x8.00mm body, 1.00mm height (max), 0.50mm pitch Symbol A A1 A3 b D D2 E E2 e L L1 θ Dimension (mm) MIN 0.80 0.00 0.20 REF 0.50 BSC 0.30 0.00 0O JEDEC Registration MO-220, Variation VLLD-2, Issue K, June 2006. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings are not to scale. Supertex Doc.#: DSPD-56QFNK68X8P050, Version A031010. Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Seating Plane Top View Side View Bottom View D E View B View B Note 3 Note 2 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) e b L A θ
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