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Technical content
Features
► HVCMOS technology for high performance ► High density integrated ultrasound transmitter ► 0 to ±60V output voltage ► ±1.0A source and sink current in pulse mode ► ±1.0A source and sink current in RTZ mode ► Up to 20MHz operating frequency ► Matched delay times ► Optional clock re-alignment ► 3.3V CMOS logic interface and reference ► +3.3V low voltage supply for VDD ► Built-in linear regulators for floating gate driver ► Built-in output drain diodes & bleed resistors Application ► Portable medical ultrasound imaging ► Piezoelectric transducer drivers ► Pulse waveform generator General Description The Supertex HV7350 is an eight channel monolithic high voltage high- speed pulse generator with built-in fast return to zero damping FETs. This high voltage and high-speed integrated circuit is designed for portable medical ultrasound image devices. HV7350 consists of a controller logic interface circuit, level translators, MOSFET gate drives, and high current power P-channel and N-channel MOSFETs as the output stage for each channel. The output peak currents of each channel are guaranteed to be over ±1.0A with up to ± 60V pulse swings as well as return-to-zero (RTZ) mode. The gate drivers for the output MOSFETs are powered by built-in linear 5.0V regulators referenced to V PP and VNN. This direct coupling topology of the gate drivers not only saves four floating voltage supplies or AC coupling capacitors per channel, but also makes the PCB layout smaller and easier. An input clock pin is available to realign all the logic input control lines to a master clock. Precise logic timing is always essential in any ultrasound systems. Typical Application Circuit Eight-Channel, High Speed, ±60V, ±1.0A, Ultrasound RTZ Pulser CPFVDD +3.3V 3.3V Logic RGND HVOUT1 VPP +10 to +60V -10 to -60V P-Driver N-Driver 1 of 8 Channels Logic Level Translator -5.0V RGND RGND DMP 1.0µF VPF VNF Rb LRP CPOS GND GNDSUB REN OEN PIN1 NIN1 PIN8 NIN8 CLK DAP LRP GND LRN GND VNF VPF LRN GND GND CNEG CNF VNN +5.0V -5.0V 1.0µF1.0µF 1.0µF1 .0µF TX1 1.0µF 1.0µF VLL +3.3V 0.1µF +5.0V
Supertex inc. www.supertex.com Doc.# DSFP-HV7350 A011314 Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Pin Configuration Package Marking L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging HV7350K6 LLLLLLLLL YYWW AAA CCC 56-Lead QFN 56-Lead QFN (top view) Package may or may not include the following marks: Si or Parameter Value VSUB, substrate voltage is GND 0V VLL, Positive logic supply -0.5V to +5.5V VDD, Positive logic and level translator supply -0.5V to +5.5V CPOS to GND, Positive level translator circuit -0.5V to +5.5V CNEG to GND, Negative level translator circuit +0.5V to -5.5V (VPP - CPF), Positive gate driver circuit -0.5V to +5.5V (CNF - VNN), Negative gate driver circuit -0.5V to +5.5V (VPP - VNN) Differential high voltage supply +130V VPP, High voltage positive supply -0.5V to +65V VNN, High voltage negative supply +0.5V to -65V All logic input PINX, NINX, OEN and REN voltages -0.5V to +5.5V Operating temperature -40°C to 125°C Storage temperature -65°C to 150°C
Ordering Information
Part Number Package Packing HV7350K6-G 56-Lead (8x8) QFN 250/ Tray HV7350K6-G M937 56-Lead (8x8) QFN 2000/Reel Typical Thermal Resistance Package θja 56-Lead (8x8) QFN 21OC/W -G denotes a lead (Pb)-free / RoHS compliant package Power-Up Sequence Step Description
1 VLL with logic signal low
2 VDD
3 REN = 1 (external supplies on)
4 VPP and VNN
5 Logic control signals active
1 All logic signals go to low
2 VPP and VNN
3 REN = 0 (external supplies off)
4 VDD
5 VLL
Note: Powering up/down in any arbitrary sequence will not cause any damage to the device. The powering up/down sequence is only recommended in order to minimize possible inrush current. Output Current & Ron ISC RonP RonN IDMP RonDP RonDN 1.5A 13Ω 6.5Ω 1.5A 13Ω 8.0Ω ESD Sensitive Device Notes: 1.VPP/VNN = +/-60V, VDD = +3.3V; REN = 1 2. ISC is current into 1.0Ω to GND; 3. IDMP is current from +/-30V connected to TX pin. 4. Max pulse width for current measurement on TX pin is 100ns.
Supertex inc. www.supertex.com Doc.# DSFP-HV7350 A011314 Operating Supply Voltages and Current (Eight Active Channels) (Operating conditions, unless otherwise specified, VLL = +3.3V, VDD = +3.3V, VPP = +60V ,VNN = -60V, VCLK = +3.3V, TA = 25°C) Sym Parameter Min Typ Max Units Conditions VDD VDD voltage supply 2.97 3.30 5.20 V --- UVLODD VDD UVLO 2.30 2.60 2.80 V --- VLL Logic voltage reference 2.50 3.30 5.00 V --- UVLOLL VLL UVLO 1.30 1.55 1.70 V --- VPP Positive high voltage supply +10 - +60 V --- VNN Negative high voltage supply -60 - -10 V --- ILLQ VLL current - 8.0 - μA OEN = REN = 0 IDDQ VDD current - 1.0 - IPPQ VPP current - 5.0 10 INNQ VNN current - 5.0 10 ILLEN VLL current - 13 20 μA OEN = REN = 1 5.0ms after f = 0MHz IDDEN VDD current - 480 700 IPPEN VPP current - 220 350 INNEN VNN current - 300 400 IDDCW VDD current - 2.3 - mA f = 5.0MHz, Continuous, no loads, for calculation reference only.I PPCW VPP current - 80 - INNCW VNN current - 80 - ILL,CLK VLL current - 33 - μA fCLK = 10MHz, PIN = NIN = 0
Electrical Characteristics
(Operating conditions, unless otherwise specified, VLL = +3.3V, VDD = +3.3V, VPP = +60V ,VNN = -60V, VCLK = +3.3V, TA = 25°C) Pulser P-Channel MOSFET Sym Parameter Min Typ Max Units Conditions IOUT Output saturation current 1.0 1.5 - A --- RON Channel resistance - 13.2 - Ω ISD = 100mA Pulser N-Channel MOSFET Sym Parameter Min Typ Max Units Conditions IOUT Output saturation current 1.0 1.5 - A --- RON Channel resistance - 8.0 - Ω ISD = 100mA Damping P-Channel MOSFET Sym Parameter Min Typ Max Units Conditions IOUT Output saturation current 1.0 1.5 - A --- RON Channel resistance - 13 - Ω ISD = 100mA Damping N-Channel MOSFET Sym Parameter Min Typ Max Units Conditions IOUT Output saturation current 1.0 1.5 - A --- RON Channel resistance - 9.0 - Ω ISD = 100mA
Supertex inc. www.supertex.com Doc.# DSFP-HV7350 A011314 Logic Inputs Sym Parameter Min Typ Max Units Conditions VIH Input logic high voltage 0.7 • VLL - VLL V VLL = 2.5 to 3.3V VIL Input logic low voltage 0 - 0.3 • VLL V VIH Input logic high voltage 0.8 • VLL - VLL V VLL = 5.0V VIL Input logic low voltage 0 - 0.2 • VLL V IIH Input logic high current - - 10 μA --- IIL Input logic low current -10 - - μA --- CIN Input logic capacitance - - 5.0 pF --- MOSFET Drain Bleed Resistor Sym Parameter Min Typ Max Units Conditions RB1~8 Output Bleed Resistance 12 17 25 kΩ --- PRB1~8 Bleed Resistors Power Limit - - 50 mW --- (Operating conditions, unless otherwise specified, VLL = +3.3V, VDD = +3.3V, VPP = +60V ,VNN = -60V, VCLK = +3.3V, TA = 25°C) Sym Parameter Min Typ Max Units Conditions tr Output rise time - 30 - ns 330pF//2.5kΩ load 10 - 90%tf Output fall time - 30 - ns tEN Enable time - 300 500 μs Cap value see page 1 diagram. OEN = RENt DIS Disable time - 2.8 10 μs td1 Delay time on PINX rise - 12 - ns 1.0Ω resistor load, D%<1% (See timing diagram) 50% inputs to 50% T X current td2 Delay time on NINX rise - 12 - td3 Delay time on damping rise - 12 - td4 Delay time on damping fall - 12 - tdc Delay time on CLK rise - 9.0 - ΔtDELAY Delay time matching - ±3.0 - ns P to N, channel to channel tj Delay jitter on rise or fall - TBD - ps VPP/VNN = +/-25V, input tr 50% to HVOUT tr or tf 50%, with 330pF//2.5kΩ load trr RTZ FETs drain diode trr - 25 - ns IF = 1.0A, IR = 1.0A, RL = 10Ω fCLK Re-timing clock frequency 10 220 - MHz --- tRC, tFC Re-timing clock rise & fall times - 0.5 5.0 ns --- tsu Set-up time, PIN/NIN to CLK 2.0 - - ns --- tH Hold time, CLK to PIN/NIN 1.0 - - ns --- tCLK_LO Clock time low 2.0 - 100 ns CLK input must have at least one pulse before PIN and NIN inputs are not zero. Be sure to return inputs to zero before stopping clock. t CLK_HI Clock time high 2.0 - 100 ns tCLK_REC Clock recognition time - 2.0 - ns tCLK_RLS Clock release time 150 300 800 ns fOUT Output frequency range - - 20 MHz 100Ω resistor load HD2 Second harmonic distortion - -40 - dB COSS Output capacitance - 50 - pF VDS = 25V, f = 1.0MHz , of TX pin total
Supertex inc. www.supertex.com Doc.# DSFP-HV7350 A011314 Switching Time Diagram CLK PINn (NINn = 0) NINn (PINn = 0) NINn (PINn = 0) CLKC LK CLK TXn TXn 0ATXn0 A 50% 50% 50% 50% td1 td4 td2 td3IOUT IOUT IOUT IOUT tdc tdc tdc tdc 50% 50% 0A 0ATXn Synchronous Mode Asynchronous Mode PINn (NINn = 0) Truth Table Logic Inputs TXn Output OEN CLK PINX NINX VPP VNN RGND Note
1 VLL 0 0 OFF OFF ON
1 VLL 1 0 ON OFF OFF
1 VLL 0 1 OFF ON OFF
1 VLL 1 1 OFF OFF OFF
clock(CLK) rising edge, registered by PIN/NIN 1 1 0 ON OFF OFF 1 0 1 OFF ON OFF 1 1 1 OFF OFF OFF
0 X X X OFF OFF OFF Disabled
Supertex inc. www.supertex.com Doc.# DSFP-HV7350 A011314 Pin Description Pin Name Description 1 PIN2 Input logic control of high voltage output P-FET for channel 2, Hi = on, Low = off. (see logic table) 2 NIN2 Input logic control of high voltage output N-FET for channel 2, Hi = on, Low = off. (see logic table) 3 PIN3 Input logic control of high voltage output P-FET for channel 3, Hi = on, Low = off. (see logic table) 4 NIN3 Input logic control of high voltage output N-FET for channel 3, Hi = on, Low = off. (see logic table) 5 PIN4 Input logic control of high voltage output P-FET for channel 4, Hi = on, Low = off. (see logic table) 6 NIN4 Input logic control of high voltage output N-FET for channel 4, Hi = on, Low = off. (see logic table) 7 OEN Output enable Hi = on, Low = off. See logic truth table 8 REN Built-in positive and negative 5V voltage regulators enable. Hi = on, Low = off. If REN = 0, exter- nal floating 5V power supplies may be supplied across CPF, CNF CPOS and CNEG capacitors 9 PIN5 Input logic control of high voltage output P-FET for channel 5, Hi = on, Low = off. (see logic table) 10 NIN5 Input logic control of high voltage output N-FET for channel 5, Hi = on, Low = off. (see logic table) 11 PIN6 Input logic control of high voltage output P-FET for channel 6, Hi = on, Low = off. (see logic table) 12 NIN6 Input logic control of high voltage output N-FET for channel 6, Hi = on, Low = off. (see logic table) 13 PIN7 Input logic control of high voltage output P-FET for channel 7, Hi = on, Low = off. (see logic table) 14 NIN7 Input logic control of high voltage output N-FET for channel 7, Hi = on, Low = off. (see logic table) 15 PIN8 Input logic control of high voltage output P-FET for channel 8, Hi = on, Low = off. (see logic table) 16 NIN8 Input logic control of high voltage output N-FET for channel 8, Hi = on, Low = off. (see logic table) 17 VLL Logic supply voltage and reference input (+3.3V)
18 GND Logic and circuit return ground (0V)
19 VDD Positive voltage power supply (+3.3V)
20 VPP
Positive high voltage power supply (+10 to +60V)21 VPP
22 VPP
23 CPF Built-in linear voltage VPF regulator output decoupling capacitor pin, 1uF from VPP to CPF per
24 CNF Built-in linear voltage VNF regulator output decoupling capacitor pin, 1uF from CNF to VNN per
25 VNN
Negative high voltage power supply (-10 to -60V)26 VNN
27 VNN
28 TX8 T
29 RGND Damping ground and bleed resistors common return ground
30 TX7 TX pulser channel 7 output
31 RGND Damping ground and bleed resistors common return ground
32 TX6 TX pulser channel 6 output
Supertex inc. www.supertex.com Doc.# DSFP-HV7350 A011314 Pin Description (cont.) Pin Name Description
33 RGND Damping ground and bleed resistors common return ground
34 TX5 TX pulser channel 5 output
35 CNEG Built-in linear voltage -5V regulator output decoupling capacitor pin, 1.0uF from CNEG to GND 36 CPOS Built-in linear voltage +5V regulator output decoupling capacitor pin, 1.0uF from CPOS to GND
37 TX4 TX pulser channel 4 output
38 RGND Damping ground and bleed resistors common return ground
39 TX3 TX pulser channel 3 output
40 RGND Damping ground and bleed resistors common return ground
41 TX2 TX pulser channel 2 output
42 RGND Damping ground and bleed resistors common return ground
43 TX1 TX pulser channel 1 output
44 VNN
Negative high voltage power supply (-10 to -60V)45 VNN
46 VNN
47 CNF Built-in linear voltage VNF regulator output decoupling capacitor pin, 1uF from CNF to VNN per
48 CPF Built-in linear voltage VPF regulator output decoupling capacitor pin, 1uF from VPP to CPF per
49 VPP
Positive high voltage power supply (+10 to +60V)50 VPP
51 VPP
52 VDD Positive voltage power supply (+3.3V)
53 GND Logic and circuit return ground (0V)
54 CLK Re-timing register clock input. Connect to V LL to disable the re-timing function 55 PIN1 Input logic control of high voltage output P-FET for channel 1, Hi = on, Low = off. (see logic table) 56 NIN1 Input logic control of high voltage output N-FET for channel 1, Hi = on, Low = off. (see logic table) VSUB (Thermal Pad) Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be connected to GND (0V) externally
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888 www.supertex.com HV7350 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV7350 A011314 56-Lead QFN Package Outline (K6) 8.00x8.00mm body, 1.00mm height (max), 0.50mm pitch Symbol A A1 A3 b D D2 E E2 e L L1 θ Dimension (mm) MIN 0.80 0.00 0.20 REF 0.50 BSC 0.30 0.00 0O JEDEC Registration MO-220, Variation VLLD-2, Issue K, June 2006. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings are not to scale. Supertex Doc.#: DSPD-56QFNK68X8P050, Version A031010. Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Seating Plane Top View Side View Bottom View D E View B View B Note 3 Note 2 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) e b L A θ