HV7331

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Document overview

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Technical content

Features

► HVCMOS technology for high performance ► High density integrated ultrasound transmitter ► 0 to ±70V output voltage ► ±2.0A source and sink minimum pulse current ► Up to 20MHz operation frequency ► ±2.5ns matched delay times ► 2.5 to 5.0V CMOS logic interface ► Built-in output drain diode and bleed resistors ► CW/RTZ Doppler quick switching ► Two damping mode options

Applications

► Portable medical ultrasound imaging ► Piezoelectric transducer drivers ► NDT ultrasound transmission ► Pulse waveform generator General Description The Supertex HV7331 is a four-channel, monolithic, high voltage, high speed pulse generator with built in fast return to zero damping FETs. This high voltage and high-speed integrated circuit is designed for portable medical ultrasound imaging devices, and can also be used for NDT applications. The HV7331 consists of a controller logic interface circuit, level translators, MOSFET gate drives, and high current power P-channel and N-channel MOSFETs as the output stage for each channel. The peak output currents of each channel are guaranteed to be over 2.0A with up to a ±70V pulse swing. The integrated regulators for the gate drivers not only saves two floating voltage supplies, but also makes the PCB layout easier. The split common source for the P or N damping MOSFETs provide pulse or CW Doppler mode quick switch-over for cost and power savings. Typical Application Circuit Four Channel, High Speed ±70V 2.0A Ultrasound RTZ Pulser CGN TX1 RGP HVOUT RGN +VCW CW/RTZ -VCW CGP Logic & Level Translator VPP VPF VNF VNN VNN SUB VSUBDGND VNN -5.0 to -70V 1 of 4-Channels Shown VSS -5.0V CNF VDD +5.0V VPP +5.0 to +70V CPFVLL +2.5 to 3.3V VPP EN LR CW/RTZ PIN1 NIN1 AGND VPF VNF VGN RGN RGP VGP VGP VGN VSS LRN VDD RGND RGND LRP RGND

Supertex inc. www.supertex.com Doc.# DSFP-HV7331 B011513 -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Power-Up Sequence Step Description

1 VLL with logic signal low

2 VDD, VSS

3 VPP, VNN

4 Logic control signals active

1 All logic signals go to low

2 VPP, VNN

3 VDD, VSS

4 VLL

L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging HV7331K6 LLLLLLLLL YYWW AAA CCC 64-Lead QFN 64-Lead QFN (top view) Package may or may not include the following marks: Si or Parameter Value AGND, DGND and VSUB 0V VLL, Positive logic supply -0.5 to +5.5V VDD, Positive logic and level translator supply -0.5 to +5.5V VSS, Negative level translator supply +0.5 to -5.5V (VPP-VNN) Differential high voltage supply +160V VPP, High voltage positive supply -0.5 to +80V VNN, High voltage negative supply +0.5 to -80V All logic input PINX, NINX, EN and CW voltages -0.5 to +5.5V (VPP -TXn) VPP to TXn voltage difference +160V (TXn -VNN) TXn to VNN voltage difference +160V (RGP - GND) RGP to GND voltage difference -0.5 to +5.5V (RGN - GND) RGN to GND voltage difference +0.5 to -5.5V Storage temperature -65 to 150°C Note: Powering up/down in any arbitrary sequence will not cause any damage to the device. The powering up/down sequence is only recommended in order to minimize possible inrush current. Ordering Information / Availability Part Number Package Option Packing HV7331K6-G 64-Lead QFN (9.0x9.0) 260/tray Typical Thermal Resistance Package θja 64-Lead QFN 21OC/W

Supertex inc. www.supertex.com Doc.# DSFP-HV7331 B011513 Operating Supply Voltages and Current (Four Active Channels) (Operating conditions, unless otherwise specified, VLL = +3.3V, VDD = +5V, VSS = -5V, VPP = +70V, VNN = -70V, VSUB = 0V, TA = 25°C) Sym Parameter Min Typ Max Units Conditions VLL Logic voltage reference 2.25 3.3 5.25 V --- VDD Positive voltage supply 4.85 5.0 5.15 V --- VSS Negative voltage supply -5.15 -5.0 -4.85 V --- VRGP Positive voltage supply 1.0 - 5.5 V When CW/RTZ = 0 (in B-Mode) must be 0 ≤ V RGP ≤ +0.5V and 0 ≥ VRGN ≥ -0.5VVRGN Negative voltage supply -5.5 - -1.0 V VPP Positive HV supply VDD - +70 V --- VNN Negative HV supply -70 - VSS V --- ILL VLL, Current EN = 0 - 1.0 3.0 μA --- IDDQ VDD, Current EN = 0 - 100 180 μA --- IDDEN VDD, Current EN = 1 - 2.5 6.0 mA f = 0MHz, CW/RTZ = Low RGN = RGP = 0VI SSQ VSS Current EN = 0 - 10 20 μA ISSEN VSS Current EN = 1 - 2.0 6.0 mA IDDCW VDD Current EN = CW = 1 - 45 55 mA f = 5.0MHz, CW/RTZ = High RGN/RGP = ±5.0V, No Load I SSCW VSS Current EN = CW = 1 - 45 55 mA IRGPCW RGP Current EN = CW = 1 - 60 75 mA IRGNCW RGP Current EN = CW = 1 - 35 75 mA IPPQ VPP Current EN = 0 - 32 50 μA --- INNQ VNN Current EN = 0 - 32 50 μA IPPEN VPP Current EN = 1 - 290 - mA f = 5.0MHz, continuous, no loadsI NNEN VNN Current EN = 1 - 290 - mA IPPEN VPP Current EN = 1, LR = 1 - 0.25 0.5 mA f = 0MHz INNEN VSS Current EN = 1, LR = 1 - 0.25 0.5 mA IPPEN VPP Current EN = 1, LR = 0 - 32 50 μA INNEN VNN Current EN = 1, LR = 0 - 32 50 μA Logic Inputs Sym Parameter Min Typ Max Units Conditions VIH Input logic high voltage (VLL - 0.4) - VLL V --- VIL Input logic low voltage 0 - 0.4 V --- IIH Input logic high current - - 1.0 μA --- IIL Input logic low current -1.0 - - μA --- CIN Input logic capacitance - - 5.0 pF ---

Supertex inc. www.supertex.com Doc.# DSFP-HV7331 B011513

Electrical Characteristics

(Operating conditions, unless otherwise specified, VLL = +3.3V, VDD = +5.0V, VSS = -5.0V, VPP = +70V, VNN = -70V, VSUB = 0V, TA = 25°C).0 Pulser P-Channel MOSFET Sym Parameter Min Typ Max Units Conditions IOUT Output saturation current 2.0 3.3 - A --- RON Channel resistance - 4.0 5.5 Ω ISD = 100mA COSS Output capacitance - 50 - pF VDS = 25V, f = 1.0MHz Pulser N-Channel MOSFET Sym Parameter Min Typ Max Units Conditions IOUT Output saturation current 2.0 3.3 - A --- RON Channel resistance - 2.3 3.0 Ω ISD = 100mA COSS Output capacitance - 50 - pF VDS = 25V, f = 1.0MHz MOSFET Drain Bleed Resistor Sym Parameter Min Typ Max Units Conditions RP/N1~4 Output bleed resistance 120 - 190 kΩ --- PRO Bleed resistors power limit - - 40 mW --- Damping P-Channel MOSFET Sym Parameter Min Typ Max Units Conditions IOUT Output saturation current 2.0 3.3 - A VRGP = VRGN = 0V RON Channel resistance - 3.7 4.8 Ω ISD = 100mA COSS Output capacitance - 50 - pF VDS = 25V, f = 1.0MHz Damping N-Channel MOSFET Sym Parameter Min Typ Max Units Conditions IOUT Output saturation current 2.0 3.3 - A VRGP = VRGN = 0V RON Channel resistance - 2.7 3.5 Ω ISD = 100mA COSS Output capacitance - 50 - pF VDS = 25V, f = 1.0MHz CW Mode P- & N-Channel MOSFET Sym Parameter Min Typ Max Units Conditions RONCW-P CW Mode ON-resistance - 14 - Ω ISD = 100mA, VRGP = +5.0V, VRGN = -5.0VRONCW-N CW Mode ON-resistance - 14 - Ω ΔRONCW P- & N-Ch RONCW matching - ±2.0 - Ω (Operating conditions, unless otherwise specified, VLL = +3.3V, VADD = VDD = +5.0V, VSS = -5.0V ,VPP = +70V, VNN = -70V, TA = 25°C) Sym Parameter Min Typ Max Units Conditions tr1 Pulser output rise time - 15 18 ns 330pF//2.5kΩ loadtf1 Pulser output fall time - 15 18 ns tr2 Damping output rise time - 15 18 ns tf2 Damping output fall time - 15 18 ns tr3 CWD output rise time - 17 22 ns 330pF//2.5kΩ load, RGP/RGN = ±5.0Vt f3 CWD output fall time - 17 22 ns

Supertex inc. www.supertex.com Doc.# DSFP-HV7331 B011513 (Operating conditions, unless otherwise specified, VLL = +3.3V, VADD = VDD = +5.0V, VSS = -5.0V ,VPP = +70V, VNN = -70V, TA = 25°C) Sym Parameter Min Typ Max Units Conditions fOUT Output frequency range - - 20 MHz 100Ω loadHD2 Second harmonic distortion - -40 - dB tEN_ON Delay on mode change - 200 300 μs CPF, CNF capacitor 0.47μF per pin, 50% to 90% t EN_OFF Chip disable time - 2.0 4.0 μs tLR_ON Linear regulators enable time - 200 300 μs tLR_OFF Linear regulators disable time - 2.0 4.0 μs tdrp1 Pulser delay time on P-rise 8.0 - 13 ns CW/RTZ = 0 R 1 = R2 = 1.0Ω to GNDtdfp1 Pulser delay time on P-fall 5.0 - 10 ns tdrn1 Pulser delay time on N-rise 8.0 - 13 ns tdfn1 Pulser delay time on N-fall 5.0 - 10 ns tdrp2 CWD delay time on P-rise 6.0 - 12 ns CW/RTZ = 1 R 1 = R2 = 1.0Ω to GNDtdfp2 CWD delay time on P-fall 6.0 - 12 ns tdrn2 CWD delay time on N-rise 6.0 - 12 ns tdfn2 CWD delay time on N-fall 6.0 - 12 ns ΔtDELAY Delay time matching - ±2.5 - ns P to N, channel to channel tJCW Delay jitter on rise or fall - 13 - ps VRGP/VRGN = ±5.0V, input tr 50% to HVOUT tr or tf 50%, with 50Ω load Inputs Output MOSFETs Operation Mode EN CW/RTZ PIN NIN VPP to TX VNN to TX TX to RGP TX to RGN B-Mode with RTZ 1 0 0 0 OFF OFF ON ON 0 1 0 ON OFF OFF OFF 0 0 1 OFF ON OFF OFF 0 1 1 OFF OFF OFF OFF CW-Mode 1 1 0 0 OFF OFF OFF OFF 1 1 0 OFF OFF ON OFF 1 0 1 OFF OFF OFF ON 1 1 1 OFF OFF OFF OFF Disable 0 X X X OFF OFF OFF OFF Logic Control Table (each channel) Note: When CW/RTZ = 0 (in B-Mode) must be 0 ≤ VRGP ≤ +0.5V and 0 ≥ VRGN ≥ -0.5V When CW/RTZ = 1 (in CW-Mode) must be 0 ≤ VRGP ≤ +5.5V and 0 ≥ VRGN ≥ -5.5V

Supertex inc. www.supertex.com Doc.# DSFP-HV7331 B011513 Switch Timing and Delay Test PINn NINn TXn 90% CW/RTZ = 0 10% 90% 10% 90% 10% PINn NINn TXn tf2tr1 tf1 tr2 tr3 tf3 CW/RTZ = 0 CGN TX1 RGP RGN CGP Logic & Level Translator VPP VPF VNF VNN VNN SUB VSUBDGND VNN -5.0 to -70V 1 of 4-Channels Shown VSS -5.0V CNF VDD +5.0V VPP +5.0 to +70V CPFVLL +2.5 to 3.3V VPP EN LR CW/RTZ PIN1 NIN1 AGND VPF VNF VGN RGN RGP VGP VGP VGN VSS LRN VDD RGND RGND LRP RGND 0 to +5.0V 0 to -5.0V 50% tdfp1 IOUT TXn 0A 50% 50% 50% 50% 50% 50%CW/RTZ = 0 PINn * Note: CW/RTZ = 1, RGP = +5.0V, RGN = -5.0V n = 1, 2, 3, 4 tdrp1 CW/RTZ = 0 NINn CW/RTZ = 1 PINn CW/RTZ = 1 NINn tdfn1tdrn1 TXn 0A TXn 0A TXn 0A IOUT IOUT IOUT tdfp2tdrp2 tdfn2tdrn2 * Note: CW/RTZ = 0, RGP = RGN = 0V

Supertex inc. www.supertex.com Doc.# DSFP-HV7331 B011513 Pin Description Pin Name Description

1 EN Chip power enable Hi = ON, Low = OFF

2 CW/RTZ B-Scan or CWD mode control pin, see Control Logic Table

3 NIN1 Input logic control signal for channel 1

4 PIN1 Input logic control signal for channel 1

5 NIN2 Input logic control signal for channel 2

6 PIN2 Input logic control signal for channel 2

7 AGND Digital logic circuit ground (0V)

8 NIN3 Input logic control signal for channel 3

9 PIN3 Input logic control signal for channel 3

10 NIN4 Input logic control signal for channel 4

11 PIN4 Input logic control signal for channel 4

12 VDD Positive voltage power supply (+5.0V)

13 LR Built-in linear regulators power turned on (enabled) when LR = 1 and EN = 1

Built-in linear regulators power turned off (disabled) when EN = 0 or LR = 0

14 VDD

Positive voltage power supply (+5.0V)

15 VDD

16 VLL Logic “1” voltage reference input (+2.5 to +5V)

17 AGND Digital logic circuit ground (0V)

18 VDD Positive voltage power supply (+5.0V)

19 DGND Driver and level translator circuit ground return (0V)

20 VSS Negative voltage power supply (-5.0V) 21 CPF VPP to VPF decoupling capacitor (low voltage, 0.22 to 0.47μF 10V) See Note 1

22 VPP

Positive high voltage power supply (+5.0 to +70V)

23 VPP

24 CGP CGP to RGP decoupling capacitor (low voltage, 0.47μF 10V) 25 RGP Common return ground or positive CW power supply. When CW/RTZ = 0 (in B-Mode) must be 0 ≤ V RGP ≤ +0.5V. When CW/RTZ = 1 (in CW-Mode) must be 0 ≤ VRGP ≤ +5.5V. 26 RGP 27 CGN CGN to RGN decoupling capacitor (low voltage, 0.47μF 10V) 28 RGN Common return ground or positive CW power supply. When CW/RTZ = 0 (in B-Mode) must be 0 ≥ V RGN ≥ -0.5V. When CW/RTZ = 1 (in CW-Mode) must be 0 ≥ VRGN ≥ -5.5V. 29 RGN 30 CNF VNF to VNN decoupling capacitor (low voltage, 0.22 to 0.47μF 10V) See Note 1

31 VNN

Negative high voltage power supply (-5.0 to -70V)

32 VNN

33 TX4

Transmit pulser output for channel 4

34 TX4

Supertex inc. www.supertex.com Doc.# DSFP-HV7331 B011513 Pin Description (cont.) Pin Name Description

35 RGND

Bleeding resistor common return ground

36 RGND

37 TX3

Transmit pulser output for channel 3

38 TX3

39 RGND

Bleeding resistor common return ground

40 RGND

41 RGND

42 RGND

43 TX2

Transmit pulser output for channel 2

44 TX2

45 RGND

Bleeding resistor common return ground

46 RGND

47 TX1

Transmit pulser output for channel 1

48 TX1

49 VNN

Negative high voltage power supply (-5.0 to -70V)

50 VNN

51 CNF VNF to VNN decoupling capacitor (low voltage, 0.22 to 0.47μF 10V) See Note 1

52 RGN

Common return ground or negative CW power supply. (0V or -1.0 to -5.5V)

53 RGN

54 CGN CGN to RGN decoupling capacitor (low voltage, 2.2μF 10V)

55 RGP

Common return ground or positive CW power supply.(0V or +1.0 to +5.5V)

56 RGP

57 CGP CGP to RGP decoupling capacitor (low voltage, 2.2μF 10V)

58 VPP

Positive high voltage power supply (+5 to +70V)

59 VPP

60 CPF CGP to RGP decoupling capacitor (low voltage, 0.22 to 0.47μF 10V) See Note 1 61 VSS Negative voltage power supply (-5.0V)

62 DGND Driver and level translator circuit ground return (0V)

63 VDD Positive voltage power supply (+5.0V)

64 AGND Digital logic circuit ground (0V)

(Thermal Pad) VSUB Substrate connect to ground (0V) Note 1: To minimize the rush-in current, nominal capacitor values for the CPF to VPP pins and the CNF to VNN pins should not exceed 0.47μF.

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com HV7331 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV7331 B011513 64-Lead QFN Package Outline (K6) 9.00x9.00mm body, 1.00mm height (max), 0.50mm pitch Seating Plane Top View Side View Bottom View D E View B View B Note 3 Note 2 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) e b L A θ Symbol A A1 A3 b D D2 E E2 e L L1 θ Dimension (mm) MIN 0.80 0.00 0.20 REF 0.50 BSC 0.30 0.00 0O JEDEC Registration MO-220, Variation VMMD-4, Issue K, June 2006. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings are not to scale. Supertex Doc.#: DSPD-64QFNK69X9P050, Version B020112 Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square.