HV732

HV732 SUTEX | Alldatasheet

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Technical content

Features

HVCMOS technology for high performance 0 to ±100V output voltage ±2A source and sink current Built-in damping for RTZ waveform capability Gate-clamp for quick output amplitude ramping Up to 40MHz operation frequency ±3ns matched delay times Second harmonic is less than -40dB 1.8V to 3.3V CMOS logic interface 7x7 thermally-enhanced 44-lead QFN MCM Application Medical ultrasound imaging General Description The Supertex HV732 is a single, complete, high-voltage, high-speed, ultrasound transmitter pulser. It is designed for medical ultrasound imaging applications. The HV732 has built-in damping for faster RTZ waveform capability and high voltage MOSFET gate-clamping function for quick ramping of the output voltage amplitude. The HV732 consists of a control logic circuit, level translators, MOSFET gate drive buffers, clamp circuits, and high current, high voltage MOSFETs as the ultrasound transmitter pulser output stage. In the output stage there are two pairs of MOSFETs. Each pair consists of a P-channel and an N-channel MOSFET. They are designed to have the same impedance, and can provide peak currents of over ±2 amps. The built-in MOSFET gate driver outputs swing 0 to 12V on P DR and NDR pins. The P-channel damp output swings 0 to –5V on the DMPO pin. Typical Application Circuit Level Trans.DAMP Level Trans. +12V Level Trans. +12V VSUB Substrate, PAD1 +5 to 12VVDD AGND VLL VLN CLAMP EN GND +1.8 to 3.3V -5V on/off Clamp Circuit N IN AVDD Bias PIN PDR TXN VNN TXP VPP OUTN OUTP RGNDP DMPINDR DMPONGATE PGATE 10nF 0 to +100V 0 to -100V HVOUT PAD3 PAD2 RGNDN 10nF 10nF Buffer Buffer

Ordering Information

-G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value VLL, logic supply -0.5V to +5.5V VDD, positive gate drive supply -0.5V to +15V AVDD, positive gate drive supply -0.5V to +15V VLN, Negative gate drive supply -5.5V to +0.5V VPP-VNN, differential high voltage supply +220V VPP, high voltage positive supply -0.5V to +200V VNN, high voltage negative supply +0.5V to -200V Storage temperature -65°C to 150°C Thermal enhanced package power dissipation 1.5W Symbol Parameter Min Typ Max Units Conditions Operating Supply Voltages and Current (Over recommended operating conditions unless otherwise specifi ed: AVDD = VDD = 12V, VLL = 3.3V, VLN = -5V, TA = 25°C) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Power-Up Sequence 1V PP and VSUB 2V NN 3V LN 4V DD 5V LL VLL Logic supply 1.8 3.3 3.6 V --- AVDD Positive analog supply 9.0 - 12.6 V --- VDD Positive drive supply 9.0 - 12.6 V --- VPP High voltage positive supply for HVOUTP1 0 - 100 V --- VNN High voltage negative supply for HVOUTN1 -100 - 0 V --- VLN High voltage negative supply for HVOUTN2 -4.75 -5.0 -5.25 V --- VSUB High voltage positive supply for to bias substrate -- 1 0 0 V Need to be the most positive supply on the device IDDQ VDD current EN = Low - 175 290 μA --- IDDEN VDD current EN = High - 1.7 2.8 mA P IN = NIN = Low IDDEN VDD current at 5MHz PW - 7.5 - mA f = 5.0MHz, PW D% = 1.0% No cap on PDR, NDR IPPQ VDD current EN = Low - 2.0 5.0 μA V PP = +100V, VNN = -100V IPPEN VDD current EN = High - 140 180 μA P IN = NIN = Low, VPP = +100V, VNN = -100V INNQ VDD current EN = Low - -1.0 -3.0 μA V PP = +100V, VNN = -100V

INNEN VDD current EN = High - -140 -180 μA P IN = NIN = Low, VPP = +100V, VNN = -100V ILLQ VDD current EN = Low - 1.0 5.0 μA --- ILLEN VDD current EN = High - 16 25 μA P IN = NIN = Low ILNQ VDD current EN = Low - -1.0 -5.0 μA --- ILNEN VDD current EN = High - -230 -320 μA P IN = NIN = Low Operating Supply Voltages and Current (cont.) (Over recommended operating conditions unless otherwise specifi ed: AVDD = VDD = 12V, VLL = 3.3V, VLN = -5V, TA = 25°C) Symbol Parameter Min Typ Max Units Conditions (Over recommended operating conditions unless otherwise specifi ed: AVDD = VDD = 12V, VLL = 3.3V, VLN = -5V, TA = 25°C) Symbol Parameter Min Typ Max Units Conditions Output P-Channel MOSFET, TXP IOUT Output saturation current -2.0 - - A V GS = -10V, VDS = -25V RON Channel resistance - - 8 Ω V GS = -10V, IDS = -1.0A RGS Gate to source resistor 10 - 50 KΩ I GS = -100μA VGS Source to gate zener voltage -13.2 - -25 V I GS = -2.0μA VGSF Gate zener forward voltage -0.5 - -0.8 V --- VGS(th) Gate threshold voltage -1.0 - -2.4 V I DS = -1.0mA CISS Input capacitance - - 200 pF VGS = 0V, VDS = -25V, f = 1Mhz COSS Output capacitance - 25 55 pF Output N-Channel MOSFET, TXN IOUT Output saturation current 2.0 - - A V GS = -10V, VDS = -25V RON Channel resistance - 7.0 Ω V GS = -10V, IDS = -1.0A RGS Gate to source resistor 10 - 50 KΩ I GS = -100μA VGS Source to gate zener voltage 13.2 - 25 V I GS = -2.0μA VGSF Gate zener forward voltage 0.5 - 0.8 V --- VGS(th) Gate threshold voltage 1.0 - 2.0 V I DS = -1.0mA CISS Input capacitance - - 110 pF VGS = 0V, VDS = -25V, f = 1Mhz COSS Output capacitance - 28 60 pF Symbol Parameter Min Typ Max Units Conditions Output P-Channel Damp MOSFET, OUTP IOUT Output saturation current - -1.0 - A V GS = -10V, VDS = -25V RON Channel resistance - - 30 Ω V GS = -10V, IDS = -1.0A RGS Gate to source resistor - 75 100 KΩ I GS = -100μA VGS Source to gate zener voltage -13.2 - -25 V I GS = -2.0μA VGSF Gate zener forward voltage 0.5 - 0.8 V --- VGS(th) Gate threshold voltage -1.0 - -2.6 V I DS = -1.0mA CISS Input capacitance - - 200 pF VGS = 0V, VDS = -25V, f = 1Mhz COSS Output capacitance - - 60 pF Symbol Parameter Min Typ Max Units Conditions

Output N-Channel Damp MOSFET, OUTN IOUT Output saturation current 1.0 - - A V GS = 10V, VDS = 25V RON Channel resistance - - 22 Ω V GS = 10V, IDS = 0.5A VGS Source to gate zener voltage 1.0 - 2.6 V I DS = 1.0μA CISS Input capacitance - - 110 pF VGS = 0V, VDS = 25V, f = 1Mhz COSS Output capacitance - - 60 pF Symbol Parameter Min Typ Max Units Conditions P-Channel Gate Driver Output, PDR RSINK Output sink resistance - 10 15 Ω I PDR = 100mA RSOURCE Output source resistance - 8.0 13 Ω I PDR = -100mA IPDR Peak output sink current - 2.0 - A --- IPDR Peak output source current - -2.0 - A --- Symbol Parameter Min Typ Max Units Conditions N-Channel Gate Driver Output, NDR RSINK Output sink resistance - 8.0 13 Ω I NDR = 100mA RSOURCE Output source resistance - 9.0 14 Ω I NDR = -100mA INDR Peak output sink current - 1.0 - A --- INDR Peak output source current - -1.0 - A --- Symbol Parameter Min Typ Max Units Conditions P-Channel Gate Driver Output, DMPO RSINK Output sink resistance - 26 30 Ω I DMPO = 100mA RSOURCE Output source resistance - 15 30 Ω I DMPO = -100mA IDMPO Peak output sink current - 0.3 - A --- IDMPO Peak output source current - -0.3 - A --- Symbol Parameter Min Typ Max Units Conditions P-Channel Gate Clamp MOSFET IOUT Output saturation current - 100 - A --- RON Channel resistance - 60 80 Ω --- COSS Output capacitance - 40 - pF V GS = 0V, VDS = 25V, f = 1Mhz Symbol Parameter Min Typ Max Units Conditions N-Channel Gate Clamp MOSFET IOUT Output saturation current - 50 - A --- RON Channel resistance - 25 50 Ω --- COSS Output capacitance - 40 - pF V GS = 0V, VDS = 25V, f = 1Mhz Symbol Parameter Min Typ Max Units Conditions

tirf Inputs rise and fall time - - 10 ns Logic input edge speed requirement VIH Input logic high voltage 0.8V LL -V LL V --- VIL Input logic low voltage 0 - 0.2V LL V --- IIH Input logic high current - - 1.0 μA --- IIL Input logic low current -1.0 - - μA --- Symbol Parameter Min Typ Max Units Conditions (Over recommended operating conditions unless otherwise specifi ed: AVDD = VDD = 12V, VLL = 3.3V, VLN = -5V, TA = 25°C) fout Output frequency range - - 40 MHz See test curcuit and timing diagram tr Output rise time - 10 - ns See relevant test circuit and timing diagram. Load = 1.0kΩ/220pF tf Output fall time - 10 - ns tdr Delay time on rise time - 12 - ns tdf Delay time on fall time - 12 - ns Δtdelay Delay time matching - - ±3.0 ns From device to device HD2 Second harmonic distortion - -40 - dB 100Ω resistor load tjitter Output jitter - 80 - ps Standard deviation of t d samples (1k) tEN Enable time - 30 50 μs See timing diagram tDMPON(P) Damp switch on delay (P) - 17 22 ns OUTP 50Ω to -15V, 10nF from DMPO to DMPI. See timing diagram.tDMPOFF(P) Damp switch off delay (P) - 20 26 ns tDMPON(N) Damp switch on delay (N) - 13 17 ns OUTN 50Ω to +15V. See timing diagram.tDMPOFF(N) Damp switch off delay (N) - 13 17 ns tCLPON(P) Clamp switch on delay (P) - 430 1000 ns PGATE 75Ω to 0V, 10nF to PDR, VPP = +12V. See timing diagram.tCLPOFF(P) Clamp switch off delay (P) - 490 1000 ns tCLPON(N) Clamp switch on delay (N) - 330 550 ns NGATE 75Ω to 0V, 10nF to NDR, VNN = -12V. See timing diagram.tCLPOFF(N) Clamp switch off delay (N) - 316 500 ns tPWRUP Device power-up delay - 150 200 μs All power supplies up and stable Symbol Parameter Min Typ Max Units Conditions Truth Table Logic Control Inputs Gate Drive Output HV Output Damp Output EN P IN NIN CLAMP DAMP P DR NDR DMPO TX P TXN OUTP OUTN 1 0 0 0 0 H L H OFF OFF OFF OFF 1 1 000 L LH ON OFF OFF OFF 10 1 00H H H OFF ON OFF OFF

1 XX1 0 H L H OFF OFF OFF OFF

0 X X X X H L H OFF OFF OFF OFF

Trans.DAMP Level Trans. +12V Buffer Level Trans. +12V Buffer VSUB +5 to 12V VDD AGND VLL VLN CLAMP EN GND +1.8 to 3.3V -5V on/off Clamp Circuit N IN AVDD Bias PIN PDR TXN VNN TXP VPP OUTN OUTP DMPINDR DMPONGATE PGATE 10nF 10nF 10nF HVOUT0V RLOAD 100 Substrate, PAD1 PAD3 PAD2 RGNDP RGNDN HV732 TX Switching Time Test 10nF 10nF 10nF 0 to +100V 0 to -100V HVOUT -5V +3.3V +12V to Oscilloscope RL 20MHz 3V0-P 10Ω +100V CL 220pFDAMP VSUBVDD PIN AGND VLL VLN CLAMP EN GND NIN AVDD PDR TXN VNN TXP VPP OUTN OUTP RGNDP DMPINDR DMPONGATE PGATE RGNDN HV732

0.175mA 2mA 1.5mA 30Us

HV732 DAMP Switching Time Diagram HV732 Clamp Switching Time Diagram tDMPON(N) 50% 10% 50% 90% DAMP DAMPOUT tDMPOFF(N) VNN tDMPON(P) 50% 10% 50% 90% tDMPOFF(P) 0VVPP tCLPON(P) 50% 10% 50% 90% CLAMP HVOUT tCLPOFF(P) VNN tCLPON(N) 50% 10% 50% 90% tCLPOFF(N) 0VVPP HV732 TX Switching Time Diagram tdr 50% 10% 50% 90% PIN NIN tdf HVOUT VNN VPP tr 10% 90% tf 90% 10%

1 DMPO Output of low voltage drive buffer for P-channel damp, 10nF external cap to pin 34 (DMPI)

2 GND Drive power ground

DR Output of low voltage drive buffer for N-DMOS, 10nF external cap to pin 9 (NGATE) 4V DD Positive voltage supply for drive circuitry (+12V)

5 VDD Positive voltage supply for drive circuitry (+12V)

SUB Substrate connection of control / driver die chip (connected to the most positive supply, VPP)

7 RGND N Ground return of damp N-DMOS source

8 OUT N Output of damp N-DMOS drain (open drain output)

9 NGATE Gate input of the high voltage N-DMOS, 10nF external cap from pin 3 (N DR)

10 V NN Negative high voltage power supply (-100V)

11 V NN Negative high voltage power supply (-100V)

12 V NN Negative high voltage power supply (-100V)

13 V NN Negative high voltage power supply (-100V)

14 V NN Negative high voltage power supply (-100V)

15 TX N Output of the high voltage N-DMOS drain (open drain output)

16 TX N Output of the high voltage N-DMOS drain (open drain output)

17 NC No connection

P Output of the high voltage P-DMOS drain (open drain output)

19 TX P Output of the high voltage P-DMOS drain (open drain output)

20 V PP Positive high voltage power supply (+100V)

21 V PP Positive high voltage power supply (+100V)

22 V PP Positive high voltage power supply (+100V)

23 V PP Positive high voltage power supply (+100V)

24 V PP Positive high voltage power supply (+100V)

25 PGATE Gate input of the high voltage P-DMOS, 10nF external cap from pin 31 (P DR)

26 OUT P Damp P-DMOS drain (open drain output)

27 RGND P Ground return of damp P-DMOS

28 V SUB Substrate connection of control / driver die chip (connected to the most positive supply, VPP)

29 V DD Positive voltage supply for drive circuitry (+12V)

30 V DD Positive voltage supply for drive circuitry (+12V)

31 P DR Output of low voltage drive buffer for P-DMOS, 10nF external cap to pin 25 (PGATE)

32 GND Drive power ground

33 GND Drive power ground

34 DMPI Connects to damp power P-DMOS gate, 10nF cap to pin 1 (DMPO)

35 P IN Input logic control of the high voltage P-DMOS pin 18 &19 (TXP), Hi = on, Low = off

36 V LN Negative low voltage power supply (–5V)

37 AV DD Positive analog voltage power supply (+12V)

38 AGND Analog signal ground (0V)

SUB Substrate connection of control / driver chip (connected to the most positive supply)

40 EN Control / drive chip power enable Hi = on, Low = off

41 DAMP Input of damp control on both pin 26 (OUT

P) and pin 8 (OUTN), Hi = on, Low = off

42 CLAMP Input of clamp switches on both gates of output P-DMOS and N-DMOS, Hi = on, Low = off

43 V LL Positive voltage supply of low voltage logic (+1.8V to +5V)

44 N IN Input logic control of the high voltage N-DMOS pin 15 & 16 (TXN), Hi = on, Low = off

Note: The three thermal slabs on the bottom of the package must be externally connected PAD1 to VSUB, PAD2 to TXN, and PAD3 to TXP.

Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 222-8888 / FAX: (408) 222-4895 www.supertex.com ©2006 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell its products for use in s uch applications, unless it receives an adequate "product liability indemnification insurance agreement". Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and spe cifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http//www.supertex.com. Doc.# DSFP - HV732 NR040506 HV732 44-Lead QFN (K6) Package Outline (The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) 1.77 [.070] 1.57 [.062]TYP 0.36 [.014] 0.26 [.010] 1.77 [.070] 1.57 [.062]TYP 0.53 [.021] 0.48 [.019] 0.28 [.011] 0.23 [.009] 0.45 [.018] 0.35 [.014] 0.38 [.015] 0.28 [.011] 0.51 [.020] 0.41 [.016] 3.35 [.141] 3.37 [.133] 4.40 [.173] 4.20 [.165] 0.74 [.029] 0.69 [.027] 7.13 [.281] 6.87 [.271] 7.13 [.281] 6.87 [.271] PAD2 PAD3 12 22 Note: 1. Dimensions in mm. [Inch] 2. Radius is 0.127mm 3. Three thermal slabs on the bottom of the package must be externally connected PAD1 to V SUB, PAD2 to TXN, and PAD3 to TXP. 0.05 [.002] 0.00 [.000] 1.00 [.039] 0.85 [.033] (N) (P) Top View PAD1