HV7224

HV7224 SUTEX | Alldatasheet

Document overview

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Technical content

Features

❏ Processed with HVCMOS® technology ❏ Symmetric row drive (reduces latent imaging in ACTFEL displays) ❏ Output voltage up to 240V ❏ Low-power level shifting ❏ Source/Sink current 70mA (min.) ❏ Shift Register Speed 3MHz ❏ Pin-programmable shift direction (DIR, SHIFT) ❏ Hi-Rel processing available Absolute Maximum Ratings Supply voltage, VDD 1 -0.5V to +7V Supply voltage, VPP -0.5V to +260V Logic input levels -0.5V to V DD +0.5V Continuous total power dissipation 2 Plastic 1200mW Ceramic 1900mW Operating temperature range Plastic -40 °C to +85°C Ceramic -55°C to +125°C Storage temperature range -65 °C to +150°C Lead temperature 1.6mm (1/16 inch) 260 °C from case for 10 seconds Notes: 1. All voltages are referenced to GND. 2. For operation above 25 °C ambient derate linearly to maximum operating tem- perature at 20mW/°C for plastic and at 19mW/°C for ceramic.

Symbol Parameter Min Max Units Conditions IDD VDD supply current 10 mA f CLK = 3MHz IPP High voltage supply current 2.0 mA Outputs low or High-Z 4.0 mA One Output High 1 IDDQ Quiescent VDD supply current 100 µA All VIN = GND or VDD VOH High-level output HV OUT 190 V I O= -70mA Data out 4.5 V I O= -100µA VOL Low-level output HV OUT 50 V I O= 70mA Data out 0.5 V I O= 100µA IIH High-level logic input current 1.0 µAV IH = VDD IIL Low-level logic input current -1.0 µAV IL = 0V ISAT Saturation current HVOUT P-Ch -80 mA N-Ch 75 mA Note: 1. Only one output can be turned on at a time.

Electrical Characteristics

(over recommended operating conditions of VDD = 5V, VPP = 240V, and TA = 25°C unless noted) DC Characteristics Symbol Parameter Min Max Units Conditions fCLK Clock frequency 3.0 MHz tW (H/L) Pulse width - clock high or low 150 ns tSUD Data set-up time before clock rises 50 ns tHD Data hold time after clock rises 50 ns tSUC HVOUT delay from clock rises (Hi-Z to H or L) 1.0 µsC L = 330pF // RL = 10kΩ tSUE HVOUT delay from Output Enable falls 600 ns C L = 330pF // RL = 10kΩ tHC HVOUT delay from clock rises (H or L to Hi-Z) 2.0 µsC L = 330pF // RL = 10kΩ tHE HVOUT delay from Output Enable rises 600 ns C L = 330pF // RL = 10kΩ tDHL * Delay time clock to data output falls 250 ns C L = 15pF tDLH * Delay time clock to data output rises 250 ns C L = 15pF tONF HVOUT fall time 2.0 µsC L = 330pF // RL = 10kΩ tONR HVOUT rise time 2.0 µsC L = 330pF // RL = 10kΩ tPOW POL pulse width 3.0 µs tOEW Output Enable pulse width 3.0 µs Slew rate, VPP or GND 45 V/ µs One active output driving 4.7nF load AC Characteristics * The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There i s an internal delay for the data output which is equal to tWH. Therefore the delay is measured from the trailing edge of the clock. HV7224

(Logic) VPP GND (Power) HV OUT Logic Inputs GND (Logic) Data Out Logic Data Output High Voltage Outputs VDD Symbol Parameter Min Max Units VDD Logic supply voltage 4.5 5.5 V VPP High voltage supply† 0 240 V VIH High-level input voltage 0.7 V DD VDD V VIL Low-level input voltage 0 0.2V DD V fCLK Clock frequency 3 MHz IO High voltage output current ±70 mA TA Operating free-air temperature Plastic -40 +85 °C Ceramic -55 +125 °C IOD Allowable pulse current through output diode ±300 mA Notes: † Output will not switch at VPP = 0V. Power-up sequence should be the following: 1. Connect ground. 2. Apply V DD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply V PP. 5. The V PP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. Recommended Operating Conditions Input and Output Equivalent Circuits

(DRIOA/DRIOB) 50% 50% tPOW Data Reset Output (DRIOA/DRIOB) tHD 50% 50% VIH VIL High Impedance 90% 10% 10% HVOUT HVOUT 90% tSUE tONR 90% tHE 10% 50% tDLH 50% tDHL 50% tOEW 50% High ImpedanceHigh Impedance High Impedance 90% 10% 10% 90% tSUC tONR 90% tHC 10% HVOUT (POL = H) HVOUT (POL = L) POL OE Data Valid tSUD Data Valid CLK tWL l/fCLK 50% 50% 50% 50% tWH tSUC tONF tHC tSUE tONF tHE VIH VIL VOH VOH VOL VIH VIL VOL VIH VIL VOH VOL

DIR Shift Data Reset In Data Reset Out HV OUT# Sequence Direction* Option (See pin-out on P. 12-158) LL D R IOB DRIOA 1 40 → 1A HL D R IOA DRIOB 2 1 → 40 A LH D R IOB DRIOA 1 20 → 1 → 40 → 21 B HH D R IOA DRIOB 2 21 → 40 → 1 → 20 B Functional Block Diagram I/O Relations Inputs CLK DIR S/R Data POL OE HV Outputs O/P HIGH X X H H L H O/P OFF X X L X L HIGH-Z O/P LOW X X H L L L O/P OFF X X X X H All O/P HIGH-Z Function Table * Reference to package outline or chip layout drawing. 1.DRIOA is DRIOBdelayed by 40 clock pulses. 2. DRIOB is DRIOA delayed by 40 clock pulses. Output Sequence Operation Table Notes: H = logic high level, L = logic low level, X = irrelevant Data input (DR IO) loaded on the low-to-high transistion of the clock. Only one active output can be set at a time. HVOUT1 HVOUT 2 HVOUT 40 OE CLK S/R DIR Polarity SHIFT P LT N LT LT GND LT = Level Translator VDD VPP DIOA DIOB

Option A: Pin Function Pin Function 1H V OUT1/40 33 N/C 2H V OUT 2/39 34 DR IOB 3H V OUT 3/38 35 OE 4H V OUT 4/37 36 NC 5H V OUT 5/36 37 POL 6H V OUT 6/35 38 N/C 7H V OUT 7/34 39 V DD 8H V OUT 8/33 40 N/C 9H V OUT 9/32 41 GND (Logic)

10 HV OUT 10/31 42 GND (Power)

11 HV OUT 11/30 43 N/C

12 HV OUT 12/29 44 V PP

13 HV OUT 13/28 45 HV OUT 21/20

14 HV OUT 14/27 46 HV OUT 22/19

15 HV OUT 15/26 47 HV OUT 23/18

16 HV OUT 16/25 48 HV OUT 24/17

17 HV OUT 17/24 49 HV OUT 25/16

18 HV OUT 18/23 50 HV OUT 26/15

19 HV OUT 19/22 51 HV OUT 27/14

20 HV OUT 20/21 52 HV OUT 28/13

21 V PP 53 HV OUT 29/12

22 N/C 54 HV OUT 30/11

23 GND (Power) 55 HV OUT 31/10

24 GND (Logic) 56 HV OUT 32/9

25 DIR 57 HV OUT 33/8

26 V DD 58 HV OUT 34/7

27 CLK 59 HV OUT 35/6

28 N/C 60 HV OUT 36/5

29 SHIFT 61 HV OUT 37/4

30 N/C 62 HV OUT 38/3

31 DR IOA 63 HV OUT 39/2

32 N/C 64 HV OUT 40/1

Note: Pin designation for DIR H/L, SHIFT = L. Example: For DIR = H, pin 1 is HV OUT1. For DIR = L, pin 1 is HVOUT40. Pins 65–80 are NC (ceramic only). Pin Configurations HV72 Option B: Pin Function Pin Function 1H V OUT 20/21 33 N/C 2H V OUT 19/22 34 DR IOB 3H V OUT 18/23 35 OE 4H V OUT 17/24 36 N/C 5H V OUT 16/25 37 POL 6H V OUT 15/26 38 N/C 7H V OUT 14/27 39 V DD 8H V OUT 13/28 40 N/C 9H V OUT 12/29 41 GND (Logic)

10 HV OUT 11/30 42 GND (Power)

11 HV OUT 10/31 43 N/C

12 HV OUT 9/32 44 V PP

13 HV OUT 8/33 45 HV OUT 40/1

14 HV OUT 7/34 46 HV OUT 39/2

15 HV OUT 6/35 47 HV OUT 38/3

16 HV OUT 5/36 48 HV OUT 37/4

17 HV OUT 4/37 49 HV OUT 36/5

18 HV OUT 3/38 50 HV OUT 35/6

19 HV OUT 2/39 51 HV OUT 34/7

20 HV OUT 1/40 52 HV OUT 33/8

21 V PP 53 HV OUT 32/9

22 N/C 54 HV OUT 31/10

23 GND (Power) 55 HV OUT 30/11

24 GND (Logic) 56 HV OUT 29/12

25 DIR 57 HV OUT 28/13

26 V DD 58 HV OUT 27/14

27 CLK 59 HV OUT 26/15

28 N/C 60 HV OUT 25/16

29 SHIFT 61 HV OUT 24/17

30 N/C 62 HV OUT 23/18

31 DR IOA 63 HV OUT 22/19

32 N/C 64 HV OUT 21/20

Note: Pin designation for DIR L/H, SHIFT = H. Example: For DIR = L, pin 1 is HV OUT20. For DIR = H, pin 1 is HVOUT21. Pins 65–80 are NC (ceramic only).

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 02/06//02 ©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. HV7224 Index 25 40 top view 3-sided Plastic 64-pin Gullwing Package Package Outline 1 24 4164 Index top view 80-pin Ceramic Gullwing Package