HV7100

HV7100 SUTEX | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 7

Technical content

Features

/boxshadowdwn High-side drive allows use of tachs /boxshadowdwn Direct interface to host controller /boxshadowdwn Noise-immune linear speed control /boxshadowdwn 4-bit digital speed control /boxshadowdwn Operates from single +24V/+48V supply /boxshadowdwn Programmable PWM frequency /boxshadowdwn Undervoltage lockout

Applications

/boxshadowdwn 24V/48V chassis cooling tray /boxshadowdwn Servers /boxshadowdwn SAN equipment /boxshadowdwn Cellular and fi x wireless systems /boxshadowdwn 24V/48V PBX system /boxshadowdwn Base stations General Description The HV7100 is an integrated PWM speed controller for driving 24V and 48V DC Fans. The features and benefi ts provided by the HV7100 make driving fans simple and low cost. The HV7100 drives a high side external P-channel FET, allowing the use of fans having a ground-based tachometer signal. It has a wide input voltage range of +16V to +90V, ideal for +24V or +48V systems. No low voltage supply is needed. A 4-bit digital control input provides direct interfacing with a microcontroller or system processor to control the fan speed. It can also be used as a stand-alone fan controller, via a thermistor connection to the Linear Control pin. The HV7100 has a wide PWM frequency range. When driving fans directly with a PWM supply voltage, frequency may be set low, around 50Hz - 120Hz. When used to drive fans requiring a DC supply, an LC fi lter may be employed. In this case, PWM frequency may be as high as 100kHz, reducing component sizes in the fi lter. The HV7100 is an ideal device to incorporate in fan trays and fan control modules, as it reduces circuit complexity and minimizes parts count and overall cost for thermal management. Typical Application Circuit 24V/48V Fan Driver/Controller With High-Side Drive VPP Host Controller DIN0 - DIN3 EN VGATE OUT GNDVDD VPP1 HV7100 LIN CT RT tach signals speed control enable VPP2 Optional LC filter for providing a DC fan drive.

Ordering Information

-G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings VPP to GND -0.5V to 90V VDD to GND -0.3V to +6V Input Voltage, LIN -0.3V to (V DD + 0.3V) Input Voltage , DIN0-DIN2 -0.3V to (V DD + 0.3V) GATE to VPP +0.5V to -15V Continuous Power Dissipation (TA = +25°C) 14-Lead SO 750mW Operating Temperature Range -40°C to +85°C Storage Temperature Range -65°C to +150°C Symbol Parameter Min Typ Max Units Conditions

Electrical Characteristics

(Operating specifi cations are at TA = 25°C, VPP = 16V to 75V, VDD = 3.0V to 5.5V, unless otherwise noted) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifi cations is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Supplies IPP VPP supply current - - 4 mA No ext load on VDD, fOSC = 50kHz, 250pF on OUT pin UVPP(ON) VPP UVLO turn-on threshold 11.7 13.0 14.3 V --- UVPP(HYS) VPP UVLO hysteresis 1.5 2.0 2.5 V --- VDD VDD internal regulation 3.0 3.3 3.6 V V PP = 16V to 75V IDD(INT) VDD supply current - - 2 mA External applied VDD = 5.0V, fOSC = 50kHz IDD(EXT) Current available from internal VDD regulator for external circuitry --2 m A ∆ V DD<200mV Symbol Parameter Min Typ Max Units VDD Externally applied VDD 3.7 - 5.5 V VPP High voltage supply 16 - 75 V fOSC Oscillator frequency 50 - 100k Hz RT Oscillator timing resistor 12 - 500 kΩ Recommended Operating Conditions

VGATE Gate regulator output voltage -10.2 -12 -13.8 V Referenced to V PP VOUTH Gate drive output voltage high -10.2 -12 -13.8 V Referenced to VPP, test current = 15mA VOUTL Gate drive output voltage low 0 - -0.8 V RSRC Pull-up resistance - - 25 Ω Test Current = 15mA RSINK Pull-down resistance - - 25 Ω Test Current = -15mA tRISE Rise time - - 100 ns C LOAD = 250pF tFALL Fall time - - 100 ns C LOAD = 250pF Oscillator fOSC Oscillator frequency 51 60 69 Hz C T = 100nF, RT = 43.0kohm fOSC Oscillator frequency 34 40 46 kHz C T = 330pF, RT = 19.5kohm Logic and Linear Inputs VDIN0-3(hi), VEN(hi) Logic input voltage, high 0.7xV DD - - V --- VDIN0-3(lo), VEN(lo) Logic input voltage, low - - 0.3xV DD V --- TEN(ON) Enable to gate turn on delay 0 - 150 ns LIN = VDD, DIN0 - DIN3 = 1111 TEN(OFF) Enable to gate turn off delay 0 - 150 ns LIN = VDD, DIN0 - DIN3 = 1111 IDIN0-3 Digital input pull down resistance 200 330 460 kΩ --- ILIN Linear control input current -1 - 1 uA -40C to +85C Duty Cycle D Duty cycle 16 20 24 % V LIN = 0.9V, DIN = 0000 D Duty Cycle 75 80 85 % V LIN = 2.1V, DIN=0000 D Duty Cycle 16 20 24 % V LIN = 0V, DIN = 0011 D Duty Cycle 75 80 85 % V LIN = 0V, DIN = 1100 D Duty Cycle - - 0 % V LIN = 0V, DIN = 0000 D Duty Cycle 100 - - % V LIN = 0V, DIN = 1111 Symbol Parameter Min Typ Max Units Conditions

VDD – Output of an internal linear voltage regulator, which in turn is powered by V PP. It provides power to the internal low-side (ground referenced) circuitry. An external voltage may be applied to this pin, provided it is higher than 3.6V but less than 5.5V. Bypass this pin with a 100nF ceramic capacitor to ground. V PP1 & VPP2 – Supply voltage pins. Both must be connected to the supply voltage (+24V/+48V). Connect together as close as possible to the IC. Bypass locally with a ceramic capacitor to ground. OUT – This pin is the output gate driver for an external P- channel power MOSFET. GND – Ground return for all the internal circuitry. This pin must be electrically connected to the ground of the power train and logic return. LIN – A DC voltage ranging from 0.5V to 2.5V sets the duty cycle of the gate output from 0% to 100%. This input is immune to moderate noise on the control signal. DIN0 - DIN3 – Applying 0000 to 1111 to these logic input pins sets the duty cycle of the gate output from 0% to 100%. A 1-bit increment is equal to 6.67% increment in duty cycle. See Table 1 on page 5. C T – In conjunction with R T, a capacitor from this pin to ground sets PWM frequency. A triangle wave appears on this pin, with an amplitude of 0.5V - 2.5V and at the PWM frequency. VDD LIN DIN0 EN OUT VPP2 VGATE RT CT GND DIN1 DIN2 DIN3 VPP1 HV7100 RT – In conjunction with CT, a resistor from this pin to ground sets PWM frequency. VGATE – This is the output pin of the internal linear regulator that biases the gate drive circuit. Bypass with 100nF ceramic capacitor to V PP. EN – Enable input. A logic high applied to this input enables the output. 14-Lead SO (NG) Package ramp gen ideal diodes Reg VPP level translator EN UVLO GND DAC Reg3.3V VDD VGATE LIN CT RT OUT DIN0-3 powered by VDD -G n d powered by VPP -V GATE VPP1 VPP2

an external P-channel FET to drive the 24V/48V DC fan. with duty cycle ranging from 0% to 100%. should be connected to VDD and CT connected to GND. discharge current into and out of CT. will fully turn the fan on (100% duty cycle). digital inputs (DIN0 – DIN3) for added system protection. digital inputs and LIN voltage to the PWM duty cycle. Table 1. DAC signal and LIN voltage to

DIN0 – DIN3 EN VGATE OUT GNDVDD VPP1 HV7100 LIN CT RT VPP2 The addition of an LC low pass filter converts the PWM output to a DC voltage. DC Fan Drive When using direct PWM drive to the fans, it is best to set a low PWM frequency, in the range of 50Hz -120Hz. The HV7100 controls the fans with a PWM supply voltage. However, some fans require a steady DC voltage for proper operation. In order for these fans to function properly, an LC low pass fi lter should be added to cancel the PWM output to a steady DC voltage. The LC fi lter also provides another advantage. Some fans draw large spikes of current during start-up and/or during normal operation. Without the LC fi lter, these current spikes would be drawn directly from the +24V or +48V supply, caus- ing potential conducted EMI problems. The LC fi lter prevents these spikes from occuring and/or reaching the +24V or +48V supply.

Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 222-8888 / FAX: (408) 222-4895 www.supertex.com ©2006 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell its products for use in s uch applications, unless it receives an adequate "product liability indemnification insurance agreement". Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and spe cifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http//www.supertex.com. Doc.# DSFP - HV7100 NR051506 HV7100 0 - 8 5 - 15 (4 plcs) 8.65 – 0.10 0.31 - 0.51

1.27 BSC

0.10 - 0.25 0.25 - 0.50 /onesans 0.17 - 0.25 0.40 - 1.27 Pin 1 dot area /onesans CL CL 1.25 min1.75 max Linear dimensions in millimeters. Angular dimensions in degrees. /onesans Pin 1 identifier may be a dot or chamfered edge, or both. Top View Side View End View VPP EN VGATE OUT GNDVDD VPP1 HV7100 LIN CT RT VPP2 VDD D2 Setting a Lower Speed Limit When using the linear control input, the digital control in- puts may be used to set a lower limit on the duty cycle. This is based on the fact that the higher control setting, linear or digital, dominates. In the example above, duty cycle is prevented from falling below 25% even if the linear control signal goes to 0V. 14-LEAD SO PACKAGE (NG) (NARROW BODY)