HV7022X-C

HV7022-C SUTEX | Alldatasheet

Document overview

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Technical content

Features

❏ Processed with HVCMOS® technology ❏ Symmetric row drive (reduces latent imaging in ACTFEL displays) ❏ Output voltages up to 230V ❏ Low-power level shifting ❏ Source/Sink current 70mA (min.) ❏ Shift register speed 4MHz ❏ Pin-programmable shift direction ❏ 44-lead plastic & ceramic surface-mount packages ❏ Hi-Rel processing available General Description The HV7022-C is a low-voltage serial to high-voltage parallel converter with push-pull outputs. It is especially suited for use as a symmetric row driver in AC thin-film electroluminescent (ACTFEL) displays. The HV70 offers 34 output lines, a direction (DIR) pin to give CW or CCW shift register loading, output enable (OE), and polarity (POL) control. After DATA INPUT is entered (on the falling edge of CLOCK), a logic high will cause the output to swing to V PP if POL is high, or to GND if POL is low. Package Options Absolute Maximum Ratings Supply voltage, VDD 1 -0.3V to +15V Supply voltage, VPP 1 -0.3V to +250V Logic input levels1 -0.3V to VDD +0.3V Ground current 2 1.5A Continuous total power dissipation3: Plastic 1200mW Ceramic 1500mW Operating temperature range Plastic -40 °C to +85°C Ceramic -55 °C to 125°C Storage temperature range -65 °C to +150°C Lead temperature 1.6mm (1/16 inch) 260 °C from case for 10 seconds Notes: 1. All voltages are referenced to GND. 2. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25 °C ambient derate linearly to maximum operating temperature at 25mW/ °C for plastic and at 15mW/ °C for ceramic. For Detailed circuit and application information, please refer to Application Note AN-H3.

Electrical Characteristics

(over recommended operating conditions of VDD = 12V, TA = 25°C and VPP = 230V unless otherwise noted) Symbol Parameter Min Max Units Conditions IDD VDD supply current 10 mA f CLK = 4MHz IPP High voltage supply current 4 mA 1 Output high 1 100 µA All Outputs low or High-Z 750 µA All Outputs low or High-Z (125°C) IDDQ Quiescent VDD supply current 100 µA All VIN = GND or VDD VOH High-level output HV OUT 195 V I O= -70mA (-50mA)2 Data out 11 V I O= -500µA VOL Low-level output HV OUT 30 V I O= 70mA (+50mA)2 Data out 1 V I O= 500µA IIH High-level logic input current 1 µAV IH = 12V IIL Low-level logic input current -1 µAV IL = 0V Notes: 1. The total number of ON outputs times the duty cycle must not exceed the allowable package power disspation. 2. Over military temperature range (-55 °C to 125°C). DC Characteristics Symbol Parameter Min Max Units Conditions fCLK Clock frequency 4 MHz tW Pulse duration clock high or low 125 ns tSUD Data set-up time before falling clock 100 ns tHD Data hold time after falling clock 100 ns tSUC Setup time clock low before VPP↑ or GND↓ 300 ns tSUE Setup time enable high before VPP↑ or GND↓ 300 ns tSUP Setup time polarity high or low before VPP↑ or GND↓ 300 ns tHC Hold time clock high after VPP↑ or GND↓ 500 ns tHE Hold time enable high after VPP↑ or GND↓ 300 ns tHP Hold time polarity high or low after VPP↑ or GND↓ 300 ns tDHL Delay time high to low level output from clock 150 ns C L = 10pF t DLH Delay time low to high level output from clock 200 ns C L = 10pF tTHL Transition time high to low level serial output 200 ns C L = 15pF tTLH Transition time low to high level serial output 100 ns C L = 15pF tONH High level turn-on time Q outputs from enable 500 ns I O = -50 mA,VOH =195V RL = 2 kΩ to 95V tONL Low level turn-on time Q outputs from enable 500 ns I O = 50 mA,VOH =130V RL = 2 kΩ to 30V tOFFH High level turn-off time Q outputs from enable 1000 ns I O = -50 mA,VOH =195V RL = 2 kΩ to 95V tOFFL Low level turn-off time Q outputs from enable 500 ns I O = 50 mA,VOH =130V RL = 2 kΩ to 30V Slew rate, VPP or GND 45 V/ µs With one active output driving a 4.7 nF load to V PP or GND AC Characteristics (VDD = 12V, TC = 25°C) HV7022-C

Logic Data Output High Voltage Outputs VDD Recommended Operating Conditions Input and Output Equivalent Circuits Symbol Parameter Min Max Units VDD Logic supply voltage 10.8 13.2 V VPP High voltage supply 230 V VIH High-level input voltage V DD = 10.8V 8.1 V VDD = 13.2V 9.9 VIL Low-level input voltage V DD = 10.8V 2.7 V VDD = 13.2V 3.3 fCLK Clock frequency 4 MHz TA Operating free-air temperature Plastic -40 +85 °C Ceramic -55 +125 °C IOD Allowable pulse current through output diodes ±300 mA Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply V DD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply V PP. 5. The V PP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above.

50% 50% Data Output (DIOA/DIOB) Clock 50% 50% 50% tSUD tHD VIH tWL tWH l/fCLK tTLH 90% 10% tTHL 90% 10% tDLH tDHL Data Input VIH VIL VOH VOL tSUC 10% 90% tHC VPP GND 50% 50% VIH VIL 90% POL GND 10% tSUP tHP 50%50% tSUE tHE 10% 90% 10% 90% tONL tONH tOFFL tOFFH VIH VIL VOH VOL VPP OE HVOUT HVOUT High Impedance High Impedance Switching Waveforms

LT = Level Translator P N Notes: H = logic high level, L = logic low level, X = irrelevant, ↓ = high-to-low transition, Q1 = HVOUT 1, Qn = HVOUT(n), etc. * = dependent on previous state and whether an O/P or S/R command occured. Inputs Outputs I/O Relations Shift Reg HV Outputs Data Out O/P HIGH X X H H H * H O/P OFF X X L H H * HIGH-Z * O/P LOW X X H L H * L * O/P OFF X X L L H * HIGH-Z * O/P OFF X X X X L * All O/P HIGH-Z * ↓ LX X X Q n →Qn+1 *Q 34 ↓ HX X X Q n →Qn-1 *Q 1 No ↓ XX XX * No Change No Change Functional Block Diagram Function Table CLK DIR Data POL OE Load S/R, set DIR

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 02/06//02 ©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. HV7022-C I(mA) I(mA) Volts 02 0 4 0 6 08 0 180 140 100 0 10020 40 60 80 VPP > 40V VDD = 12V & 14 V 100 180 140 100 Volts (VPP - VOUT) Temp = 25 C° Temp = 25 C° VDD = 14 VDD = 10 VDD = 12 HVOUT Characteristics Output N-Channel Characteristics through FET Output P-Channel Characteristics through FET Pin Configurations Package Outline HV70

44 Pin J-Lead Package

3H V OUT 16/19 25 Polarity 4H V OUT 15/20 26 Data In 5H V OUT 14/21 27 V PP 6H V OUT 13/22 28 N/C 7H V OUT 12/23 29 HV OUT 34/1 8H V OUT 11/24 30 HV OUT 33/2 9H V OUT 10/25 31 HV OUT 32/3

10 HV OUT 9/26 32 HV OUT 31/4

11 HV OUT 8/27 33 HV OUT 30/5

12 HV OUT 7/28 34 HV OUT 29/6

13 HV OUT 6/29 35 HV OUT 28/7

14 HV OUT 5/30 36 HV OUT 27/8

15 HV OUT 4/31 37 HV OUT 26/9

16 HV OUT 3/32 38 HV OUT 25/10

17 HV OUT 2/33 39 HV OUT 24/11

18 HV OUT 1/34 40 HV OUT 23/12

19 Data Out 41 HV OUT 22/13

20 Output Enable 42 HV OUT 21/14

21 Clock 43 HV OUT 20/15

22 GND 44 HV OUT 19/16

Note: Pin designation for DIR L/H Example:For DIR = L, pin 1 is HV OUT 18 For DIR = H, pin 1 is HV OUT 17 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 top view 44-pin J-Lead Package