HV6810_13 SUTEX | Alldatasheet

Document overview

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Technical content

Features

► High output voltage 80V ► High speed 5MHz @5.0VDD ► Low power IBB ≤ 0.1mA (all high) ► Active pull down 100µA min @25OC ► Output source current 25mA @60V VBB ► Each device drives 10 lines ► High-speed serially-shifted data input ► 5.0V CMOS-compatible inputs ► Latches on all driver outputs ► Pin-compatible replacement for UCN5810A and TL4810A, TL4810B

Applications

► High speed dot matrix print head driver ► VFD (vacuum fluorescent display) driver General Description The HV6810 is a monolithic integrated circuit designed to drive a dot matrix or segmented vacuum fluorescent display (VFD). These devices feature a serial data output to cascade additional devices for large displays. A 10-bit data word is serially loaded into the shift register on the positive-going transition of the clock. Parallel data is transferred to the output buffers through a 10-bit D-type latch while the latch enable input is high, and is latched when the latch enable is low. When the blanking input is high, all of the outputs are low. Outputs are structures formed by double-diffused MOS (DMOS) transistors with output voltage ratings of 80V and 25mA source-current capability. All inputs are compatible with CMOS levels. 10-Channel, Serial-Input Latched Display Driver Functional Block Diagram Blanking Latch Enable Q10 Data Input Clock LC1 LC2 LC9 LC10 Latches Shift Register

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6 Stages

(Q3 thru Q8 not shown Serial Out

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  • • VBB Logic Diagram (positive logic)

Supertex inc. www.supertex.com Doc.# DSFP-HV6810 E070913 Recommended Operating Conditions Sym Parameter Min Typ Max Units Conditions VDD Supply voltage 4.5 - 5.5 V --- VBB High supply voltage 20 - 80 V --- VSS Supply voltage - 0 - V --- VIH High-level input voltage (for VDD = 5.0V) 3.5 - 5.3 V --- VIL Low-level input voltage -0.3 - 0.8 V --- IOH Continuous high-level Q output current 25 - - mA --- fCLK Clock frequency - - 5.0 MHz --- TA Operating ambient temperature -40 - +85 °C --- Absolute Maximum Ratings1 Parameter Value Logic supply voltage, VDD 2 7.5V Driver supply voltage, VBB 2 90V Output voltage2 90V Input voltage2 -0.3V to VDD+ 0.3V Continuous total power dissipation at OC free-air temperature:3 20-Lead PLCC3 20-Lead SOW3 1500mW 1500mW Operating temperature range -45°C +85°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to GND. Notes: 1. Over operating free-air temperature 2. All voltages are referenced to V SS 3. For operation above 25OC ambient derate linearly to 85OC at 15mW/OC Pin Configuration Product Marking 1 20 2012 YY = Year Sealed WW = Week Sealed A = Assembler ID L = Lot Number C = Country of Origin* = “Green” Packaging * May be part of top marking Top Marking Bottom Marking YYWW AAA HV6810WG LLLLLLLLLL CCCCCCCCCCC 20-Lead PLCC 20-Lead SOW YY = Year Sealed WW = Week Sealed L = Lot Number A = Assembler ID C = Country of Origin* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW AAA HV6810PJ LLLLLLLLLL CCCCCCCCCCC 20-Lead SOW (top view) 20-Lead PLCC (top view) Package may or may not include the following marks: Si or Package may or may not include the following marks: Si or Part Number Package Options Packing HV6810PJ-G 20-Lead PLCC* 48/Tube HV6810PJ-G M910 20-Lead PLCC* 1000/Reel HV6810WG-G 20-Lead SOW 1000/Reel

Ordering Information

-G denotes a lead (Pb)-free / RoHS compliant package * Obsolescence notice issued for the product in the 20-Lead PLCC package. Typical Thermal Resistance Package θja 20-Lead PLCC 66OC/W 20-Lead SOW 66OC/W

Supertex inc. www.supertex.com Doc.# DSFP-HV6810 E070913 Sym Parameter Min Typ Max Units Conditions tW(CKH) Pulse duration, clock high 100 - - ns --- tW(LEH) Pulse duration, latch enable high 100 - - ns --- tSU(D) Setup time, data before clock 50 - - ns --- tH(D) Hold time, data after clock 50 - - ns --- tCKH-LEH Delay time, clock to latch enable high 50 - - ns --- tPD * Propagation delay time, latch enable to output - 300 - ns --- * Switching characteristics, VBB = 60V, TA = 25OC (Timing requirements over recommended operating conditions) (VDD = 5.0V, VBB = 60V, VSS = 0V, TA = 25OC unless otherwise noted) Sym Parameter Min Typ Max Units Conditions VOH High level output voltage Q outputs 57.5 58 - V IO = +25mA Serial output 4.0 4.5 - VDD = +4.5V, IOL = +100µA VOL Low level output voltage Q outputs - 0.15 1.0 V IO = -100µA, blanking input at VDD Serial output - 0.05 0.1 VDD = +4.5V, IO = -100µA IOL Low level Q output current (pull-down current) 60 80 - µA TA = Max, VOL = +0.7V IO(OFF) Off-state output current - -1.0 -15 µA VO = 0V, blanking input at VDD IIH High level input current - 1.0 µA VlN = VDD IDD Supply current from VDD (standby) - 10 50 µA All inputs at 0V, one Q output high - 10 50 All inputs at 0V, all Q outputs low I BB Supply current from VBB - 0.05 0.1 mA All outputs low, all Q outputs open - 0.05 0.1 All outputs high, all Q outputs open * All typical values are at TA = 25OC except for IOL and IO(OFF). Power-up sequence should be the following: 1. Connect ground VSS 2. Apply VDD 3. Set all inputs (Data, CLK, Enable, etc.) to a known state 4. Apply V BB The VBB should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above.

Supertex inc. www.supertex.com Doc.# DSFP-HV6810 E070913 Timing Diagram VALIDI RRELEVANT INVALID VALID PREVIOUSLY STORED DATA NEW DATA VALID VALID Clock Data In SR Contents Latch Enable Latch

Contents

tW(CKH) 50% 50% VIH VIL VIH VIL Valid 50% 50% Data Clock tH(D)tSU(D) 50% 50% 50% tCKH-LEH Valid Valid90% Clock Input Latch Enable Q Output tPD tW(LEH) Input Timing VIH VIL VIH VIL VOH VOL Output Switching Timing

Supertex inc. www.supertex.com Doc.# DSFP-HV6810 E070913 Input and Output Equivalent Circuits VDD DATA INPUT VSS Input Equivalent Circuit VDD GND DATA OUT VSS Q Logic Data Output VBB High Voltage Output Function Table Serial Data Input Clock Input Shift Register I1 I2 I3 ... IN-1 IN Serial Data Output LE Strobe Input Latch Contents I1 I2 I3 ... IN-1 IN Blanking Input Output Contents I1 I2 I3 ... IN-1 IN H H R1 R2 ... RN-2 RN-1 RN-1 --- --- --- --- L L R1 R2 ... RN-2 RN-1 RN-1 X R1 R2 R3 ... RN-1 RN RN --- --- Notes: L = Low logic level, H = High logic level, X = Don’t care, P = Present state, R = Previous state = Low to high transition = High to low transition

Supertex inc. www.supertex.com Doc.# DSFP-HV6810 E070913 Pin Description 20-Lead PLCC (PJ) Pin # Function Description 1 Q8 High voltage output.2 Q7 3 Q6 4 CLOCK Input data is shifted into the data shift register on the positive edge of the clock. 5 N/C No connection. 6 VSS Usually VSS = 0V, ground connection. 7 VDD Low voltage power supply. 8 LE (STROBE) When LE is high, the shift register output is latched to Q output. When LE stays high, the latches are in transparent mode. 9 Q5 High voltage output. 10 Q4 11 Q3 12 Q2 13 Q1

14 BLANKING When blanking is high, all Q’s are forced to a low state, regardless of data in each

channel. 15 DATA IN Input data for the input shift register. 16 N/C No connection. 17 VBB High voltage power supply. 18 SERIAL DATA OUT Output data from the shift register.

19 Q10

High voltage output. 20 Q9

Supertex inc. www.supertex.com Doc.# DSFP-HV6810 E070913 20-Lead SOW (WG) Pin # Function Description 1 Q8 High voltage output.2 Q7 3 Q6 4 CLOCK Input data are shifted into the data shift register on the positive edge of the clock. 5 VSS Usually VSS = 0V, ground connection. 6 N/C No connection. 7 VDD Low voltage power supply. 8 LE (STROBE) When LE is high, the shift register output is latched to Q output. When LE stays high, the latches are in transparent mode. 9 Q5 High voltage output. 10 Q4 11 Q3 12 Q2 13 Q1 channel. 15 DATA IN Input data for the input shift register. 16 VBB High voltage power supply. 17 SERIAL DATA OUT Output data from the shift register. 18 N/C No connection. High voltage output. 20 Q9 Pin Description

Supertex inc. www.supertex.com Doc.# DSFP-HV6810 E070913 20-Lead PLCC Package Outline (PJ) .353x.353in body, .180in height (max), .050in pitch Symbol A A1 A2 b b1 D D1 E E1 e R Dimension (inches) .050 BSC .025 JEDEC Registration MS-018, Variation AA, Issue A, June, 1993. Drawings not to scale. Supertex Doc. #: DSPD-20PLCCPJ, Version C031111 .150max .048/.042 x 45O .075max D E Top View View B A A2A1 Seating Plane Note 1 (Index Area) .056/.042 x 45O Base Plane .020min b View B Horizontal Side View Vertical Side View Note 2 .020max (3 Places) R e Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary.

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com HV6810 (The package drawings in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV6810 E070913 20-Lead SOW (Wide Body) Package Outline (WG) 12.80x7.50mm body, 2.65mm height (max), 1.27mm pitch Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1 Dimension (mm) 1.27 BSC 0.25 0.40 1.40 REF 0.25 BSC 0O 5O JEDEC Registration MS-013, Variation AC, Issue E, Sep. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-20SOWWG, Version D041309. EE1 D e b A A2 Seating Plane A A Top View Side View Note 1 (Index Area 0.25D x 0.75E1) View B View A-A Seating Plane Gauge Plane L View B θ h h Note 1 Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.