HV6810WG-G

HV6810_07 SUTEX | Alldatasheet

Document overview

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Technical content

Features

High speed 5MHz @ 5.0VDD Low power IBB ≤ 0.1mA (all high) Active pull down 100µA min Output source current 100mA at 60V V PP Each device drives 10 lines High-speed serially-shifted data input 5.0V CMOS-compatible inputs Latches on all driver outputs Pin-compatible replacement for UCN5810A and TL4810A, TL4810B

Applications

High speed dot matrix print head driver VFD (vacuum fl uorescent display) driver General Description The HV6810 is a monolithic integrated circuit designed to drive a dot matrix or segmented vacuum fl uorescent display (VFD). These devices feature a serial data output to cascade additional devices for large displays. A 10-bit data word is serially loaded into the shift register on the positive-going transition of the clock. Parallel data is transferred to the output buffers through a 10-bit D-type latch while the latch enable input is high, and is latched when the latch enable is low. When the blanking input is high, all of the outputs are low. Outputs are structures formed by double-diffused MOS (DMOS) transistors with output voltage ratings of 80V and 25mA source-current capability. All inputs are compatible with CMOS levels.

Ordering Information

20-J Lead PLCC 20-Lead SOW HV6810 HV6810PJ-G HV6810WG-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value Logic supply voltage, VDD (1) 7.5V Driver supply voltage, VBB (1) 90V Output voltage(1) 90V Input voltage(1) -0.3V to VDD+ 0.3V Continuous total power dissipation at 25OC free-air temperature 20-J Lead PLCC (PJ) 20-Lead SOW (WG) 1000mW (2) 1000mW(2) Operating temperature range -45°C +85°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifi cations is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Notes: (1) All voltages are referenced to V SS. (2) For operation above 25OC ambient derate linearly to 85OC at 16.7mW/OC. Pin Confi gurations Product Marking 10-Channel Serial-Input Latched Display Driver 201 20-Lead SOW (WG) (top view) 20-J Lead PLCC (PJ) (top view) YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV6810WG LLLLLLLLLL CCCCCCCCCCC AAA 20-J Lead PLCC (PJ) 20-Lead SOW (WG) YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV6810PJ LLLLLLLLLL CCCCCCCCCCC AAA

Recommended Operating Conditions Sym Parameter Min Typ Max Units Conditions VDD Supply voltage 4.5 - 5.5 V --- VBB Supply voltage 20 - 80 V --- VSS Supply voltage - 0 - V --- VIH High-level input voltage (for VDD = 5.0V) 3.5 - 5.3 V --- VIL Low-level input voltage -0.3 - 0.8 V --- IOH Continuous high-level Q output current -25 - - mA --- fCLK Clock frequency - - 5.0 MHz --- TA Operating ambient temperature -40 - +85 °C --- Power-Up / Power-Down Sequence Step Description

1 Connect ground V SS

2 Apply V DD

3 Set all inputs (Data, CLK, Enable, etc.) to a known state

4 Apply V

5 The V BB should not drop below VDD or fl oat during operation. Power-down sequence should be the reverse of the above. (VDD = 5V±10%, VBB = 60V, VSS = 0, TA = 25OC unless otherwise noted) Sym Parameter Min Typ Max Units Conditions VOH High level output voltage Q outputs 57.5 58 - V IOH = 25mA Serial output 4.0 4.5 - V DD = 4.5V, IOL = -100µA VOL Low level output voltage Q outputs - 0.15 1.0 V IOH = 100µA, blanking input at VDD Serial output - 0.05 0.1 V DD = 4.5V, IOL = 100µA IOL Low level Q output current (pull-down current) 60 80 - µA T A = Max, VOL = 0.7V IO(OFF) Off-state output current - -1.0 -15 µA VO = 0, Blanking input TA = Max at VDD IH High level input current - 1.0 µA V l = VDD IDD Supply current from VDD (standby) -1 0 5 0 µA All inputs at 0V, one Q output high -1 0 5 0 All inputs at 0V, all Q outputs low IBB Supply current from VBB - 0.05 0.1 mA All outputs low, all Q outputs open - 0.05 0.1 All outputs high, all Q outputs open * All typical values are at TA = 25OC except for IO.

Sym Parameter Min Typ Max Units Conditions tW(CKH) Pulse duration, clock high 100 - - ns --- tW(LEH) Pulse duration, latch enable high 100 - - ns --- tSU(D) Setup time, data before clock 50 - - ns --- tH(D) Hold time, data after clock 50 - - ns --- tCKH-LEH Delay time, clock to latch enable high 50 - - ns --- tPD * Propagation delay time, latch enable to output - 0.3 - ns --- * Switching characteristics, VBB = 60V, TA = 25OC (Timing requirements over recommended operating conditions) Switching Waveforms w(CKH)t 50% 50% VIH VIL VIH V Valid 50% 50%Data Clock h(D)tsu(D)t 50% VIH VIL VIH VIL 50% 50% CKH–LEHt Valid Valid90% Clock Input Latch Enable Output pdt w(LEH)t Input Timing Output Switching Times Timing Diagram VALID IRRELEVANT INVALID VALID PREVIOUSLY STORED DATA NEW DATA VALID VALID Clock Data In SR Contents Latch Enable Latch

Contents

Input and Output Equivalent Circuits VDD Input VSS Input Equivalent Circuit VSS Output Logic Data Output VBB Functional Block Diagram Blanking Latch Enable Q10 Data Input Clock R1 R10 LC1 LC2 LC9 LC10 LatchesShift Register    

6 Stages

(Q3 thru Q8) not shown Serial Out Function Table Serial Data Input Clock Input Shift Register I1 I2 I3 ... IN-1 IN Serial Data Output Strobe Input Latch Contents I1 I2 I3 ... IN-1 IN Blanking Input Output Contents I1 I2 I3 ... IN-1 IN HH R 1 R2 ... RN-2 RN-1 RN-1 --- --- --- --- LL R 1 R2 ... RN-2 RN-1 RN-1 XR 1 R2 R3 ... RN-1 RN RN --- --- Logic Diagram (positive logic)

HV6810 20-J Lead PLCC (PJ) Pin Function Description 1Q 8 High voltage output.2Q 7 3Q 6

4 CLOCK Input data are shifted into the data shift register on the thepostive edge of the

clock. 5 N/C No connection. 6 VSS Usually V SS = 0, ground connection. 7 VDD Low voltage power supply.

8 LE (STROBE)

When LE is high, data is transferred from data shift register to the Q output latch. When LE is low, data is latched into data latches and new data can be clocked into the shift register. 9Q 5 High voltage output. 10 Q4 11 Q3 12 Q2 13 Q1

14 BLANKING

When blanking is low, all Q’s are forced to a high state, regardless of data in each channel. When OL is low, all Q’s are forced to a low state, regardless of data in each channel. 15 DATA IN Input data for the input shift register. 16 N/C No connection. 17 VBB High voltage power supply. 18 SERIAL DATA OUT Output data from the shift register.

19 Q10

High voltage output. 20 Q9

HV6810 20-Lead SOW (WG) Pin Function 1Q 8 High voltage output.2Q 7 3Q 6 4 CLOCK Input data are shifted into the data shift register on the thepostive edge of the clock.

5 VSS Usually V

SS = 0, ground connection. 6 N/C No connection. 7 VDD Low voltage power supply. When LE is high, data is transferred from data shift register to the Q output latch. When LE is low, data is latched into data latches and new data can be clocked into the shift register 9Q 5 High voltage output. 10 Q4 11 Q3 12 Q2 13 Q1 When blanking is low, all Q’s are forced to a high state, regardless of data in each channel. When OL is low, all Q’s are forced to a low state, regardless of data in each channel. 15 DATA IN Input data for the input shift register. 16 VBB High voltage power supply. 17 SERIAL DATA OUT Output data from the shift register. 18 N/C No connection. High voltage output. 20 Q9 Pin Descriptions

20-J Lead PLCC Package Outline (PJ) Symbol A A1 A2 b b1 D D1 E E1 e Dimension (inches) .050 JEDEC Registration MS-018, Variation AA, Issue A, June, 1993. Drawings not to scale. Note 1: A Pin 1 identifi er must be located in the index area indicated.The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature. .150 MAX .048/.042 x 45O .075 MAX D E1 E Top View Side View View B A A2A1 Seating Planee Note 1 (Index Area) .056/.042 x 45O .020 MAX

3 Places

.020 MIN b View B

(The package drawings in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV6810 A101507 20-Lead SOW (Wide Body) Package Outline (WG) 12.80x7.50mm body, 2.65mm height (max), 1.27mm pitch Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1 Dimension (mm) 1.27 BSC 0.25 0.40 1.40 REF 0.25 BSC 0O 5O N O M ---- 1 2 . 8 0 1 0 . 3 0 7 . 5 0 -- -- JEDEC Registration MS-013, Variation AC, Issue E, Sep. 2005. Drawings not to scale. D Seating Plane Gauge Plane L Top View Side View View A-A View B View B θ E1 E A A2 A A Seating Plane e b h h Note 1 Note 1 (Index Area 0.25D x 0.75E1) Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifi er must be located in the index area indicated.The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature.