HV6810 SUTEX | Alldatasheet
Document overview
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Technical content
Features
nn High output voltage 80V nn High speed 5MHz @ 5VDD nn Low power IBB ≤ 0.1mA (All high) nn Active pull down 100µA min nn Output source current 100mA at 60V VPP nn Each device drives 10 lines nn High-speed serially-shifted data input nn 5V CMOS-compatible inputs nn Latches on all driver outputs nn Pin-compatible improved replacement for UCN5810A and TL4810A, TL4810B Absolute Maximum Ratings1 Logic supply voltage, VDD 2 7.5V Driver supply voltage, VBB 2 90V Output voltage2 90V Input voltage2 -0.3V to VDD + 0.3V Continuous total power dissipation 18-Pin P-DIP3 900mW at 25°C free-air temperature 3 20-Pin SOIC4 1000mW 20-Pin PLCC4 1000mW Operating Temperature Range -40 ° to +85*C Notes: 1. Over operating free-air temperature. 2. All voltages are referenced to VSS . 3. For operation above 25°C ambient derate linearly to 85°C at 15mW/°C. 4. For operation above 25°C ambient derate linearly to 85°C at 16.7mW/°C. Device 18-Pin 20-Pin Small 20-Pin Plastic Die Plastic DIP Outline Package Chip Carrier HV6810 HV6810P HV6810WG HV6810PJ HV6810X *For Hi-Rel process flow, refer to page 5-3 of the Databook.
Symbol Parameter Min Typ Max Units Conditions VOH High-level output voltage Q outputs 57.5 58 V I OH = 25mA Serial output 4 4.5 V V DD = 4.5V, IOH = -100µA VOL Low-level output voltage Q outputs 0.15 1 V I OH = 100µA, Blanking input at VDD Serial output 0.05 0.1 V V DD = 4.5V, IOL = 100µA IOL Low-level Q output current (pull-down current) 60 80 µAT A = Max, VOL = 0.7V IO(OFF) Off-state output current -1 -15 µAV O = 0, Blanking input TA = Max at VDD IH High-level input current 1 µAV I = VDD IDD Supply current from VDD (standby) 10 50 µA All inputs at 0V, one Q output high 10 50 µA All inputs at 0V, all Q outputs low IBB Supply current from VBB 0.05 0.1 mA All outputs low, all Q outputs open 0.05 0.1 mA All outputs high, all Q outputs open All typical values are at TA = 25°C, except for IO . HV6810
Electrical Characteristics
DC Characteristics (VDD = 5V ±10%, VBB = 60V, VSS = 0, TA = 25°C unless otherwise noted) Symbol Parameter Min Nom Max Units VDD Supply voltage 4.5 5.5 V VBB Supply voltage 20 80 V VSS Supply voltage 0 V VIH High-level input voltage (for VDD = 5V) 3.5 5.3 V VIL Low-level input voltage -0.3 0.8 V IOH Continuous high-level Q output current -25 mA fCLK Clock frequency 5 MHz TA Operating free-air temperature Plastic -40 +85 °C Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply V DD . 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP . Power-down sequence should be the reverse of the above. Recommended Operating Conditions AC Characteristics (Timing requirements over recommended operating conditions) Symbol Parameter Min Typ Max Units Conditions tW(CKH) Pulse duration, clock high 100 ns tW(LEH) Pulse duration, latch enable high 100 ns tSU(D) Setup time, data before clock 50 ns tH(D) Hold time, data after clock 50 ns tCKH-LEH Delay time, clock to latch enable high 50 ns tpd* Propagation delay time, latch enable to output 0.3 µs * Switching characteristics, VBB = 60V, TA = 25°C.
PREVIOUSLY STORED DATA NEW DATA VALID VALID Clock Data In SR Contents Latch Enable Latch
Contents
Input and Output Equivalent Circuits HV6810 Timing Diagram
w(CKH)t 50% 50% V IH V IL V IH V IL Valid 50% 50%Data Clock h(D)tsu(D)t 50% V IH V IL V IH V IL 50% 50% CKH–LEHt Valid Valid90% Clock Input Latch Enable Output pdt w(LEH)t HV6810 Serial Shift Register Contents Serial Latch Contents Output ContentsClock Strobe BlankingData DataInput Input InputInput I 1 I2 I3 …I N-1 IN Output I 1 I2 I3 …I N-1 IN I1 I2 I3 …I N-1 IN HH R 1 R 2 …R N-2 R N-1 R N-1 LL R 1 R 2 …R N-2 R N-1 R N-1 XR 1 R 2 R 3 …R N-1 R N R N XXX… X X X L R 1 R 2 R 3 …R N-1 R N P1 P2 P3 …P N-1 PN PN P1 P2 P3 …P N-1 PN P1 P2 P3 …P N-1 PN XXX… X X H LLL… L L LH L = Low logic level H = High logic level X = Irrelevant P = Present state R = Previous state Function Table Functional Block Diagram Input Timing Output Switching Times Switching Waveforms Blanking Latch Enable Q10 Data Input Clock R1 R10 LC1 LC2 LC9 LC10 LatchesShift Register
6 Stages
(Q3 thru Q8) not shown Serial Out Logic Diagram (positive logic)