HV66X

HV66 SUTEX | Alldatasheet

Document overview

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Technical content

Features

❏ Processed with HVCMOS® technology ❏ 32 push-pull CMOS output up to 32V ❏ Low power level shifting ❏ Source/sink current minimum 1mA ❏ Shift register speed 5MHz ❏ Latched data outputs ❏ Bidirectional shift register (DIR) ❏ Backplane output 32-Channel LCD Driver with Separate Backplane Output HV66 General Description Not recommended for new designs. The HV66 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver circuit for LCD displays. It can also be used in any application requiring multiple output high-voltage current sourc- ing and sinking capabilities. The inputs are fully CMOS compat- ible. The device consists of a 32-bit shift register, 32 latches, and control logic to perform blanking and polarity control of the outputs. HVout1 is connected to the first stage of the shift register. Data is shifted through the shift register on the logic rising transition of the clock. A DIR pin causes data shifting counter- clockwise when grounded and clockwise when connected to V DD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the LE (latch enable), BL (blank) or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) input is high. The data in the latch is stored after LE transitions from high to low. The blank signal, BL, when pulled low, will set all outputs to the same state as the BP OUT. If this signal is left open then the BL defaults to a high state.

Ordering Information

44 Lead Quad 44 J-Lead Quad Die

Plastic Gullwing Plastic Chip Carrier in waffle pack HV66 HV66PG HV66PJ HV66X Absolute Maximum Ratings1 Supply voltage, VDD 2 -0.5V to +7.0V Output voltage, VPP 2 -0.5V to +35V Logic input levels2 -0.5V to VDD + 0.5V Ground current3 1.5A Continuous total power dissipation4 1200mW Operating temperature range -40 °C to +85°C Storage temperature range -65 °C to +125°C Lead temperature 1.6mm (1/16 inch) 260 °C from case for 10 seconds Notes: 1. Device will survive (but operation may not be specified or guaranteed) at these extremes. 2. All voltages are referenced to V SS. 3. Duty cycle is limited by the total power dissipated in the package. 4. For operation above 25 °C ambient derate linearly to 85°C at 20mW/°C.

Symbol Parameter Min Max Units VDD Logic supply voltage 4.5 5.5 V VPP Output voltage* 0 32 V VIH High-level input voltage 2.4 V DD V VIL Low-level input voltage 0 0.8 V fCLK Clock frequency 0 5 MHz TA Operating free-air temperature -40 +85 °C IOD Allowable current through output diodes 200 mA Notes: *Output will not switch below 12V. Power-up sequence should be the following: 2. Apply V DD.4 . Apply VPP. Power-down sequence should be the reverse of the above. The VPP should not drop below VDD during operation. Electrical Characteristics (over recommended operating conditions unless noted) DC Characteristics (VDD = 5V, VPP = 32V, VSS = GND) Symbol Parameter Min Max Units Conditions IDD VDD supply current 15 mA V DD = VDD max fCLK = 5MHz IPPQ High voltage supply current 0.5 mA Outputs high 0.5 mA Outputs low IDDQ Quiescent VDD supply current 0.5 mA All V IN = VSS or VDD VOH High-level output Q 22 V I O= 1mA, VPP = 24V Data out 4.6 V I O= -100µA VOL Low-level output Q 2 V I O= 1mA Data out 0.4 V I O= 100µA IIH High-level logic input current 1 µAV IH = VDD IIL Low-level logic input current -1 µAV IL = 0V VOLBP Low-level output voltage, backplane 3 V I O = 10mA VOHBP High-level output voltage, backplane 29 V I O = -10mA AC Characteristics (VDD = 5V, VPP = 32V, TC = 25°C), logic input rises/fall time = 10ns. Symbol Parameter Min Max Units Conditions fCLK Clock frequency 5 MHz tW Clock width high or low 100 ns tSU Data set-up time before clock rises 25 ns tH Data hold time after clock rises 50 ns tON, tOFF Time from latch enable or POL to HVOUT 500 ns C L = 20pF tON, tOFF Time from POL to BP output 500 ns C L = 20pF tDHL Delay time clock to data high to low 200 ns C L = 10pF tDLH Delay time clock to data low to high 200 ns C L = 10pF tDLE Delay time clock to LE low to high 50 ns tWLE Width of LE pulse 100 ns tSLE LE set-up time before clock rises 50 ns tBR, tBF BPOUT rise/fall time 10 1000 µsC L = 350nF  tBR - tBF BPOUT rise and fall difference 100 µsC L = 350nF Recommended Operating Conditions HV66

Data Valid50% 50%Data Input Clock Data Out 50% 50% 50% tSU tH tWL tWH 50% 50% tDLH tDHL 50% tWLEtDLE tSLE 50% HVOUT w/ S/R HIGH 50% tOFF VIH VIL VIH VIL VOH VOL VOH VOL VIH VOL VOH VOL VOH VOL 50% tON tBR POL (ASYNCH w/ Clock) BPOUT VOHBP VOLBP 50% tBF tON 50% 50% tOFF 50% 10% 90% 50%

Function Data CLK LE BL POL DIR Shift Reg HV Outputs Data Out BP OUT 1 2…32 1 2…32 2…32 * Load latches X H or L L H H X * *…* * *…* * H R/L Shift X ↑ XHX H Qn → Qn+1 * *…* Q32 Blank X X X L L X * *…* L L…L * L Control X X X L H X * *…* H H…H * H Function Table Notes: H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition. * = dependent on previous stage’s state before the last CLK or last LE high. HVOUT1 HVOUT2 HVOUT31 HVOUT32 (Outputs 3 to 30 not shown) Polarity Blank Latch Enable Data Input Clock Data Out 32-Bit Shift Register Latch Latch Latch Latch VPP BPOUT VDD DIR GND

44 Pin Plastic Gullwing (QFP) Package

10 HV OUT13/20 32 Data In

11 HV OUT12/21 33 V PP

12 HV OUT11/22 34 BP Out

13 HV OUT10/23 35 HV OUT32/1

14 HV OUT9/24 36 HV OUT31/2

15 HV OUT8/25 37 HV OUT30/3

16 HV OUT7/26 38 HV OUT29/4

17 HV OUT6/27 39 HV OUT28/5

18 HV OUT5/28 40 HV OUT27/6

19 HV OUT4/29 41 HV OUT26/7

20 HV OUT3/30 42 HV OUT25/8

21 HV OUT2/31 43 HV OUT24/9

22 HV OUT1/32 44 HV OUT23/10

Note: Pin designation for DIR = H/L Example:for DIR = H, Pin 1 is HVOUT 22 for DIR = L, Pin 1 is HVOUT 11 Package Outline

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 02/06//02 ©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. HV66

44 Pin J-Lead Package

8H V OUT 10/23 30 HV OUT 32/1 9H V OUT 9/24 31 HV OUT 31/2

10 HV OUT 8/25 32 HV OUT 30/3

11 HV OUT 7/26 33 HV OUT 29/4

12 HV OUT 6/27 34 HV OUT 28/5

13 HV OUT 5/28 35 HV OUT 27/6

14 HV OUT 4/29 36 HV OUT 26/7

15 HV OUT 3/30 37 HV OUT 25/8

16 HV OUT 2/31 38 HV OUT 24/9

17 HV OUT 1/32 39 HV OUT 23/10

18 Data Out 40 HV OUT 22/11

19 GND 41 HV OUT 21/12

20 N/C 42 HV OUT 20/13

21 BL 43 HV OUT 19/14

22 POL 44 HV OUT 18/15

Note: 1. Pin designation for DIR = H/L Example:for DIR = H, Pin 1 = HVOUT 17 for DIR = L, Pin 1 = HVOUT 16 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 top view 44-pin PLCC HV66 Pin Configuration Package Outline