HV632

HV632 SUTEX | Alldatasheet

Document overview

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Technical content

Features

HVCMOS® technology 5V CMOS inputs Up to 80V output voltage PWM gray shade conversion Capable of 256 levels of gray shading 10MHz shift and count clock frequency 20MHz data throughput rate 8 bit data bus 32 outputs per device BLANK function Output polarity control General Description The HV632 is a 32-channel gray-shade column driver IC de- signed for driving electrofluorescent displays. Using Supertex’s unique HVCMOS® technology, it is capable of 256 levels of gray shading by PWM conversion. Input data, in groups of eight, is latched into a set of data latches on both edges of the shift clock. The data shifted in the first data latch corresponds to HVOUT1, the second data latch corresponds to HVOUT2, and so on. These data are compared to the contents of the master binary counter which counts on both edges of the count clock. Each time the master counter begins to decrement from 1111 1111, the data in the data latches are compared with the contents of the counter; if they match, the corresponding outputs will go high. The master counter counts down to 0000 0001 and then starts to count up again. The outputs that are at high will stay at high until the contents of the counter match the data in the data latches again. Therefore, the higher the binary data in the data latches, the longer the outputs will stay at high. Thus, different high voltage pulse widths are produced. When the counter reaches its 1111 1111 count while counting up, the device is ready for the next operation cycle. A data value of 0000 0000 produces no pulse; the output stays low. The BLANK input signal will reset the master counter to all ones (1111 1111) and set all high voltage outputs to low, or will set all high voltage outputs to high state, when the POL is low. The POL input signal, forced low, will invert the polarity of the output pulse. If left unconnected, POL input will be pulled high to VDD by an on- chip resistor.

Applications

❏Field Emission Displays (FED) ❏Polymer Liquid Crystal Displays (PLCD) ❏Vacuum Fluorescent Displays (VFD) DIN(1-8) SC CSO CSI LC BL CC Shift Register Latches Counter Comparators Low Voltage High Voltage HVout1 HVout32 Micro Processor Scan Driver HV57908 Colunms (Cathodes) Display Panel (FED) Supertex HV632 CSI Level Translators Push-Pull Output Buffers POL High Voltage Power Supply Low Voltage Power Supply for cascading the next HV632 HV632 Initial Release Typical Application

Ordering Information

64-Lead 3-Sided Plastic Gullwing Die HV632 HV632PG HV632X Absolute Maximum Ratings Supply voltage, VDD -0.5V to +7.5V Supply voltage, VPP -0.5V to +90V Logic input levels -0.5 to VDD + 0.5V Continuous total power dissipation 1.2W Operating temperature range -40°C to +85°C Storage temperature range -65°C to +150°C Notes: All voltages are referenced to GND. For operation above 25°C ambient derate linearly to 85°C at 20mW/°C.

Electrical Characteristics

(Over recommended conditions of VDD = 5V, VPP = 80V, TA = 25°C unless otherwise noted) Symbol Parameter Min Max Units Conditions VDD Low-voltage digital supply voltage 4.5 5.5 V IDD VDD supply current mA fSC = 10MHz, fCC = 10MHz IDDQ Quiescent VDD supply current 150 µA All VIN = GND, Count Clock = VDD IIH High-level input current µA VIN = VDD IIL Low-level input current -10 µA VIL = GND IOH High-level output current -1.0 mA VOUT=0.9 VDD IOL Low-level ouptut current 1.0 mA VOUT=0.1 VDD Low-Voltage DC Characteristics (Digital) Symbol Parameter Min Max Units Conditions IPPQ Quiescent VPP supply current 100 µA All HVOUT low or high IOUT(p) P-channel output current -4.0 mA HVOUT=75V IOUT(n) N-channel output current 4.0 mA HVOUT=5V IPP VPP supply current 1.1 mA CL=0pF, FCC=10Mhz High-Voltage DC Characteristics

(Over recommended conditions of VDD = 5V, VPP = 80V, TA = 25°C unless otherwise noted) Symbol Parameter Min Max Units Conditions fSC Shift clock frequency MHz fCC Count clock frequency MHz fDIN Data In frequency MHz tCW Chip select pulse width ns tCSS Chip select to shift clock set-up time 5.0 ns tCSH Chip select to shift clock hold time ns tSCC Shift clock cycle time 100 ns tDSS Data to shift clock set-up time ns tDSH Data to shift clock hold time ns tDW Data In pulse width ns tLCW Load count pulse width ns tCCW Count clock pulse width ns tCCC Count clock cycle time 100 ns tLCD Load count to count clock delay 100 ns tCCD Count clock to HVOUT turn-on/turn-off 300 ns CL = 15pF tBLW BLANK pulse width 700 ns tBLD BLANK to HVOUT delay 500 ns CL = 15pF tCDD Count clock delay between count down and 150 ns count up cycles tCSOH CSO delay output for High ns CL=15pF tCSOL CSO delay output for Low ns CL=15pF AC Characteristics Symbol Parameter Min Max Units Conditions VDD Logic supply voltage 4.5 5.5 V VPP Positive high-voltage supply V VIL Low-level input voltage V VIH High-level input voltage VDD–1 VDD V TA Operating temperature -40 +85 Recommended Operating Conditions Pin # Name I/O Function 27-30 D1 – D8 I Inputs for binary-format parallel data 36-39 (D8 is the most significant bit) Shift Clock I Triggers data on both edges Count Clock I Input to the counter POL I Output polarity control CSI I Chip select input to enable the device to accept data CSO O Chip select output to enable the next device Load Count I Input to initiate the counting Blank I Input to reset the counter and HVOUT 4-19 HVOUT1 – HVOUT32 O High-voltage outputs 46-61 23,43 VPP Positive high-voltage supply VDD Low-voltage digital supply voltage 22,44 HVGND High voltage ground 20-21 GND Digital ground Pin Definitions

& Latch 1 L/T Data Latch 2 Comparator & Latch 2 L/T Data Latch 3 Comparator & Latch 3 L/T Data Latch 32 Comparator & Latch 32 L/T Logic

8 Bit

L/T = Level Translator CSO CSI HVGND Logic Logic Logic Logic HVGND Load Count Shift Clock POL* * Internal pull-up resistor

Input and Output Equivalent Circuits VDD Input GND VPP HVGND HVOUT Logic Inputs GND Data Out Logic Data Output High Voltage Output VDD HVOUT Shift Clock VALID DATA CSI CSO LC Count Clock 252 253 254 255 255 254 253 252 252 253 254 255 255 254 253 252 VALID DATA Timing Diagrams

50% t CSH 50% 50% SC2 SC16 SC1 SCN DATA SET 2 DATA SET 3 DATA SET 31 DATA SET 32 DATA SET 1 t LCW tCCW t CCC tLCD VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 50% 50% 90% 10% 10% 50% 50% 50% 50% tCCD DATA SET 2 DATA SET 2N -1 BLANK tBLW tCDD VIH VIL 50% 50% 255 254 90% HVOUT tBLD VPP HVGND VIL 50% 50% VIH Data 1–8 VPP HVGND DATA SET 2N 50% 90% tCCD tCSOH t CSOL CSO VIH VIL

3-sided Plastic 64-pin Gullwing Package Pin Configurations Pin Function N/C N/C N/C HVOUT17 HVOUT18 HVOUT19 HVOUT20 HVOUT21 HVOUT22 HVOUT23 HVOUT24 HVOUT25 HVOUT26 HVOUT27 HVOUT28 HVOUT29 HVOUT30 HVOUT31 HVOUT32 GND GND HVGND VPP CSI CSO Blank Count Clock POL Pin Function Load Count Shift Clock N/C VDD NC NC VPP HVGND N/C HVOUT1 HVOUT 2 HVOUT 3 HVOUT 4 HVOUT 5 HVOUT 6 HVOUT 7 HVOUT 8 HVOUT 9 HVOUT10 HVOUT11 HVOUT12 HVOUT13 HVOUT14 HVOUT15 HVOUT16 N/C N/C N/C Package Outline

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 222-8888 • FAX: (408) 222-4895 www.supertex.com 07/08/03rev.2 ©2003 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 0° − 7° 0° – 10° REF 0.884 ± 0.004 (22.4536 ± 0.1016) D 0.547 ± 0.004 (13.8938 ± 0.1016) 0.705 ± 0.004 (17.907 ± 0.102) E 0.782 ± 0.004 (19.8628 ± 0.1016) 0.015 ± 0.003 (0.381 ± 0.0762) B 0.0315 (0.800) e 0.015 ± 0.003 (0.381 ± 0.0762) 0.040 (1.016) 0.106 ± 0.010 (2.692 ± 0.254) L 0.031 ± 0.005 (0.7874 ± 0.127) A 0.118 ± 0.010 (2.9972 ± 0.254) 64-Lead 3-Sided Plastic Quad Flat Package (PG) (“Gullwing” Package) Note: Circle (e.g. B ) indicates JEDEC Reference. Dimensions in Inches (Dimensions in Millimeters) Measurement Legend = Package Outline