HV62106

HV62106 SUTEX | Alldatasheet

Document overview

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Technical content

Features

Capable of 4 output pulse widths PWM gray shade conversion Two 2-bit data buses

28 MHz data throughput rate

Pin-programmable shift direction (DIR) Integrated high-voltage CMOS technology Optimized layout for COG use General Description Not recommended for new designs. The HV62106 is a 64-channel column driver IC designed for gray shade flat panel displays. Using Supertex’s unique HVCMOS® technology, it is capable of providing gray shading by pulse width modulation (PWM) conversion. A high level on the chip select input enables the IC to load data into a set of input data latches. This input data, in two groups of two, are latched into the input data latches on both edges of the Shift Clock. The data stored in these input data latches is transferred to a set of output data latches on the rising edge of Load Count. After the input data registers are full, a chip select output signal is provided for enabling the next IC in the chain. A master binary counter is reset with a high level on Load Count and is incremented on the rising edge of Count Clock. The data stored in the output data latches is compared to the contents of the master counter. The output of the comparator drives the high voltage output devices. The higher the binary number in the output data latches, the longer the pulse width will be on the corresponding output. DIR is a shift-direction-select input which is provided to inter- change the direction of the latched data inputs. When the DIR input is high, CS2 becomes chip select input and data is latched into the data latches in the sequence of HV OUT 1 to HVOUT 64. When the DIR input is low, CS1 becomes chip select input and data is latched into the data latches in the sequence of HV OUT 64 to HVOUT 1. DIN1 and DIN2 load in data for odd number of outputs. D IN3 and DIN4 load in data for even number of outputs.

Symbol Parameter Min Max Units Conditions fSC Shift clock frequency 7 MHz fDIN Data In frequency 7 MHz fCC Count clock frequency 3 MHz tWA Chip select pulse width 80 ns tSS Chip select set-up time 20 ns tHS Chip select hold time 40 ns tDS Data to shift clock set-up time -10 30 ns tDH Data to shift clock hold time 30 ns tWLC Load count pulse width 160 ns tDLCC Load count to count clock delay 70 ns tDSL Shift clock to load count delay 200 ns tCSC Shift clock cycle time 143 ns tDLC Load count to HVOUT delay 1.5 µsC L = 15pF // RL = 10MΩ tWCC Count clock pulse width 160 ns tCCC Count clock cycle time 333 ns tDCC Count clock to HVOUT delay 1.5 µsC L = 15pF // RL = 10MΩ tWSC Shift clock pulse width 70 ns tWD Data in pulse width 60 ns

Electrical Characteristics

(Over recommended conditions of VDD = 5V, VPP = 60V, TA = 25°C unless otherwise noted) Symbol Parameter Min Max Units Conditions IPPQ Quiescent VPP supply current 100 µA All HV OUT low or high VOH High-level output 50 V I OUT = -12mA VOL Low-level output 8 V I OUT = 15mA High Voltage DC Characteristics AC Characteristics (Logic Timing) HV62106 Symbol Parameter Min Max Units Conditions IDD VDD supply current 10 mA f SC = 7MHz, fCC = 3MHz IDDQ Quiescent VDD supply current 1 mA All V IN = GND IIH High-level input current 10 µAV IH = VDD IIL Low-level input current -10 µAV IL = GND IOH High-level output current -1 mA IOL Low-level output current 1 mA Low Voltage DC Characteristics

Sequence Function Data-In CS1/ CS2/ Shift Load Count Clock HV OUT (D1 - D4) CS2 CS1 Clock Count (RCLK, GCLK)

1 Load data from H/L X L H L

2 Load counter X L X X H

3 Counting/conversion X L X X L H/L

4 Next cycle H/L X L H L

Symbol Parameter Min Max Units Conditions V PP High voltage supply 0 60 V VDD Logic supply voltage 4.5 5.5 V VIL Low-level input voltage 0 1 V VIH High-level input voltage V DD -1 V DD V fSC Shift clock frequency 7 MHz fCC Count clock frequency 3 MHz TA Operating temperature -40 +85 °C Recommended Operating Conditions Pad Definitions HV62106 Function Table Pad # Name I/O Function 2 - 5 D IN1 - DIN4 I Inputs for binary-format parallel data 18 -21 (D IN 2 and DIN 4 are the most significant bits) 23, 33 Shift Clock I Latching data on both edges 24, 32 CS1 I/O Input when DIR = 0; Output when DIR = 1 10, 22 CS2 I/O Output when DIR = 0; Input when DIR = 1 8, 15 Load Count I Initiates the conversion 26, 30 DIR I Controls the data shift directions 27, 29 GND — Logic ground 14, 28 HVGND — High voltage ground 1, 41 V PP — High voltage supply 42-105 HV OUT 1 – 64 O High voltage outputs 25, 31 V DD — Logic supply voltage 6, 17 Count Clock I Input for incrementing the master counter for the green pixel (GCLK) 7, 16 Count Clock I Input for incrementing the master counter for the red pixel (RCLK)

Logic Data Output High Voltage Outputs VDD HVGND Comparator2 Comparator2 Comparator2 Comparator2 HV OUT 1 HV OUT 3 HV OUT 5 HV OUT 2 HV OUT 4 HV OUT 6 HV OUT 63 VPP L/T L/T L/T L/T HV OUT 64 Count Clock (GCLK, RCLK) Data Latch Data Latch Data Latch Data Latch Load Count Data Latch Data Latch Data Latch Data Latch DIR Shift Clock L/T = Level Translator CS1 D IN (3, 4) DIN (1, 2) Logic Logic Logic Logic CS2 Functional Block Diagram Input and Output Equivalent Circuits HV62106

Current Loading Cycle Next Loading Cycle Shift Clock Load Count Count Clock (RCLK, GCLK) HV OUT 50% 90% 50% 50% 10% 50% 50% 50% 50% SET SET SET SET SET SET SET SET SET SET 123 1 6 12 Current Loading Cycle Next Loading Cycle CS1/2 Shift Clock Data In CS2/1 Shift Clock Data In SET SET SET 16 1 2 SET ≈≈ ≈ ≈≈≈ ≈≈≈ SET SET tWA tHS tWSC tWD tSS tDHtDS tCSC tWLC tDSL tDLCC tCCC tDLC tDCC tWCC Timing Diagrams HV62106