HV610 SUTEX | Alldatasheet
Document overview
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Technical content
Features
HVCMOS® technology Operating output voltage up to +50/-40V Shift register speed 40MHz @ V DD = 5V Data speed up to 160MHz @ VDD = 5V 32 high voltage outputs CMOS/TTL compatible
Applications
High speed print head driver LCD driver 32-Channel Serial to Parallel Converter With High Voltage Push-Pull Outputs Typical Application Diagram General Description The HV610 is a 32-channel high voltage, medium current driver IC. The outputs can be either at V PPS, V NN, HiZ, or HVGND. Data is shifted through four parallel 8-bit shift registers on the low to high transition of the clock. A data output buffer is provided for cascading devices. Data is transferred to a 32-bit latch when logic level high is applied to the LE input. The CLR signal will reset both the shift register and the latch. Output states are controlled by POS, and NEG input signals, and by data in the latch. All outputs are tri-stated upon a logic high on the HiZ input signal. HV610 LCD or Piezo Array Level Translators Decoder Logic
32 HV Buffers
DIN(1-4) DOUT (1-4) HVOUT1 HVOUT32 GND VDD VPPSVPPLT HVGNDVNN 50V 50V -40V Host Controller
Ordering Information
10x10x1.20mm body, 0.50mm pitch HV610 HV610FG-G Absolute Maximum Ratings Parameter Value Supply voltage, VDD -0.5V to 6V Supply voltage, VPP 55V Supply voltage, VNN -45V Logic input levels -0.5V to V DD+0.5V Operating junction temperature range -40°C to +125°C Storage temperature range -65°C +150°C All voltages referenced to GND. Operating Supply Voltages and Temperatures (All voltages referenced to GND) Symbol Parameter Min Typ Max Units Conditions VDD Logic supply voltage 4.5 5.0 5.5 V --- VPPS Positive high voltage supply for HVOUTPUT source 25 - 50 V For f OUT = 200kHz VPPLT Positive high voltage supply for level translators 47.5 - 50 V --- VNN Negative high voltage supply -15 - -40 V For f OUT = 200kHz HVGND High voltage ground -5 - +5 V --- VIH High-level input voltage 2.0 - V DD V --- VIL Low-level input voltage 0 0.8 V --- TA Operating ambient temperature -40 - +85 °C --- -G indicates package is RoHS compliant (‘Green’) Pin Confi guration 64-Lead TQFP (top view) Product Marking YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV610FG LLLLLLLLL CCCCCCCC AAA
Symbol Parameter Min Typ Max Units Conditions Over operating supply voltages and temperature, unless otherwise noted. IDD VDD supply current - - 15 mA f CLK = 40MHz IDDQ VDD quiescent supply current - - 0.1 mA All logic inputs = VDD or 0V - - 2.2 Per each input at TTL level IPPS VPPS supply current - - 412 mA CL = 700pF, fOUT = 200kHz, all channels switching per HVOUT waveform IPPSQ VPPS quiescent supply current - - 100 µA VPPS = 50V, outputs static, VPPLT = 50V IPPLT VPPLT supply current - - 17 mA f OUT = 200kHz IPPLTQ VPPLTQ quiescent supply current - - 100 µA VPPS = 50V, outputs static, VPPLT = 50V INN VNN supply current - - 433 mA CL = 700pF, fOUT = 200kHz, all channels switching per HVOUT waveform INNQ VNN quiescent supply current - - 100 µA V NN = -40V, outputs static IIH Logic input high current - - 50 µA V IH = VDD - - 50 µA V IH = 2.0V IIL Logic input low current - - -50 µA VIL = 0V IOL DOUT low level logic sink current - - 12 mA D OUT < 0.8V IOH DOUT high level logic source current - - -12 mA DOUT > 2.0V VOH High level output HVOUT VPPS -10 - - V IHVOUT = -35mA, VPPS = +50V, VPPLT = +50V, VNN = -40V DOUT VDD -1.0 - - ID OUT = -15mA VOL Low level output HVOUT -- V NN +10 V IHVOUT = 35mA, VPPS = +50V, VPPLT = +50V, VNN = -40V DOUT - - 1.0 ID OUT = 15mA VOMID Mid level output -10 - 10 V IMID = ±35mA, VPPS = +50V, VPPLT = +50V, VNN = -40V CDIN LV input capacitance - - 10 pF --- Over operating supply voltages and temperature, unless otherwise noted. Symbol Parameter Min Typ Max Units Conditions fCLK Clock frequency 0- 4 0 MHz 0 toVDD clock input 0 - 33 0 to 2.0V clock input fOUT Output switching frequency switching waveform - - 200 KHz CL = 700pf, 5% to 95% VPPLT = 50V tC Clock high/low pulse width 10 - - ns 0 - VDD logic signals 10 - - 0 - 2.0V logic signals
Over operating supply voltages and temperature, unless otherwise noted. Symbol Parameter Min Typ Max Units Conditions tSUD Data setup time before clock rises 12.5 - - ns 0 - VDD logic signals 15 - - 0 - 2V logic signals tHD Data hold time after clock rises 2 - - ns --- tSUC LE from CLK setup time 15 - - ns --- tLE LE pulse width 10 - - ns --- tWOC Width of CLR, POS, NEG, HiZ pulses 500 - - ns --- tDHiZ HiZ input to HVOUT HiZ state delay - - 400 ns --- tCLRH CLR input to HVOUT delay - - 1.1 µs --- tDCLR CLR input to DOUT delay 5 - 50 ns --- tDD Clock positive edge to DOUT delay 2.5 - 12.5 ns C LDOUT = 30pF tPHV Delay time from inputs for HV OUT to start rise/fall - - 500 ns V PPLT = 50V tHiZ Output HiZ state before each transi- tion - - 100 ns V PPLT = 50V tHR Time for output to go from 95% of VPPS/VNN to 99% of VPPS/VNN - - 0.5 µs CL = 700pF, HVGND to VPPS, or HVGND to VNN transitions - - 1.0 µs CL = 700pF, VPPS to VNN, or VNN to VPPS transitions tHG Time for output to go from HVGND ± 1V to within 1% of HVGND - - 0.5 µs CL = 700pF, VNN to HVGND, or VPPS to HVGND transitions tRPN, tFPN Output rise/fall time (per function table3) - - 1.6 µs CL = 700pF, VPPLT = 50V, transi- tions between VPPS and VNN tRR, tFR Output rise/fall time from HV GND to 95% of VPPS/VNN - - 0.9 µs CL = 700pF, V PPLT = 50V tRG, tFG Output rise/fall time from 95% of VPPS/VNN to HVGND ±1V - - 0.9 µs CL = 700pF, V PPLT = 50V tORPN, tOFPN Delay time from input edges to 95% of HV OUT rise/fall (per function table 3) - - 1.8 µs CL = 700pF, VPPLT = 50V, transi- tions between VPPS and VNN tORG, tOFG Delay time from input edges to 95% of HV OUT rise/fall from HV GND to V PPS or VNN, or from VPPS/VNN to within ±1V of HVGND - - 1.1 µs CL = 700pF, VPPLT = 50V, transitions between V PPS/VNN and HVGND θJA Thermal resistance, junction to ambient -5 9- OC/W Mounted on 4-layer PCB board
Function Table 1 (S/R and DOUT of S/R one of four) Inputs Outputs Data (n-1) CLK CLR LE, POS, NEG, HiZ S/R1...8(n)* Data Out L or H L to H L X S/R1 = DIN(n-1) S/R2 = S/R1(n-1) S/R8 = S/R7(n-1) S/R8(n-1) X L L X S/R1..8(n-1) D OUT(n-1) X H L X S/R1..8(n-1) D OUT(n-1) XXH X L L Notes: H = high level, L = low level, X = irrelevant, IN1 to DIN4 => 1st S/R1..8 to 4th S/R1..8, Function Table 2 (Latch) Inputs Outputs D1..32 LE CLR CLK, POS, NEG, HiZ LD1..32 XXHXL L or H H L X L or H X L L X Unchanged Function Table 3 (HV outputs) Inputs Outputs POS NEG HiZ CLK LE CLR D IN LD1..32 HV OUT1..32 XXHXXXXX H i Z HHLXL LXH H i Z LLLXLLXX H V G N D X X L X L L X L HVGND LHLXLLXH V NN HLLXLLXH V PPS X X L X X H X X HVGND
8 Bit
32 Bit
Input and Output Equivalent Circuits VDD Input DGND Logic Inputs DGND Data Out Logic Data Output High Voltage Outputs VDD HVGND HVOUT VNN VPPS
Data Valid50% 50% t SUC t LE t SUD tHD tC tDD tDCLR tCLRH DIN CLK CLR LE DOUT VIH VIL VIH VIL VIH VIL VIH VIL tPHV 95% 95% tPHV tPHV tFPN tRG tRR tORG tORG tOFPN 50% 50% 50% tWOC 95% 95% tRPN tFR tORPN tOFG tOFG tFG HVGnd - 1V HVGnd + 1V 50% 50%50% tHR tHR tHR tHR tHG tHG tPHV tPHV tPHV tCLRH CLK CLR POS NEG HVOUT HVOUT VIH VIL VIH VIL VIH VIL VPPS HVGND VNN VPPS HVGND V NN VNN VPPS HVGND tDHiZ VIH VIL HVOUT HiZ
10 HV OUT15
11 HV OUT14
12 HV OUT13
13 HV OUT12
14 HV OUT11
15 HV OUT10
16 V NN
17 HVGND
19 HV OUT9
20 HV OUT8
21 HV OUT7
22 HV OUT6
23 HV OUT5
24 HV OUT4
25 HV OUT3
26 HV OUT2
27 HV OUT1
28 V NN
29 V PPS
30 HVGND
32 D IN1
33 D IN2
34 D IN3
35 D IN4
36 DGND
37 POS
38 NEG
39 HIZ
40 CLK
41 CLR
44 DGND
47 D OUT3
48 D OUT2
49 D OUT1
50 V PPLT
51 HVGND
53 V NN
54 HV OUT32
55 HV OUT31
56 HV OUT30
57 HV OUT29
58 HV OUT28
59 HV OUT27
60 HV OUT26
61 HV OUT25
62 HV OUT24
63 V PPS
64 HVGND
Pin # Function Pin # Function Pin # Function Pin # Function Power-Up / Power-Down Sequence Step Description
1 Connect DGND and HVGND
2 Apply V DD
3 Set all inputs (Data, CLK, LE, POS, NEG, HiZ, etc.) to a known state
4 Apply V NN
5 Apply V PPLT
6 Apply V PPS
Power-down sequence should be the reverse of the above. To insure the safest power-up/down sequence, the intervals between power-up signals should be between 1msec to 10msec, after the previous signal changed 95% of its fi nal level.
(The package drawings in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Seating Plane Gauge Plane θL View B View B Seating Plane Top View D EE1 b e Side View A2A Note 1 (Index Area D1/4 x E1/4) Doc.# DSFP-HV610 NR061107 Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ Dimension (mm) 0.50 BSC 0.45 1.00 REF 0.25 BSC JEDEC Registration MS-026, Variation ACD, Issue D, Jan. 2001. Drawings not to scale. Note 1: A Pin 1 identifi er must be located in the index area indicated. The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature. 64-Lead TQFP Package Outline (FG) 10x10mm body, 1.2mm height (max.), 0.50mm pitch