HV5812 SUTEX | Alldatasheet
Document overview
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Technical content
Features
❏ Operating voltage of to up to 80V ❏ HVCMOS technology for high performance ❏ High speed source driver ❏ Up to 3.3MHz data input rate ❏ 5.0V CMOS logic circuitry ❏ Excellent noise immunity ❏ Flexible high voltage supplies
Symbol Parameter Min Typ Max Units Conditions IDSS Output leakage current -5.0 -15 µAV OUT = 0V, TA = +70°C HVOH Output voltage 78 78.5 V IOUT = -25mA, VPP = 80V TA = +25°C HVOH Output Voltage 77 78 V IOUT = -25mA, VPP = 80V TA = +125°C HVOL Output Voltage V DD = 5V 1.5 3.0 V I OUT = 1.0mA, TA = +25°C HVOL Output Voltage V DD = 5V 2.3 4.0 V I OUT = 1.0mA, TA = +125°C ISINK Output pull-down current V DD = 5V 2.0 3.5 mA V OUT = 5.0V to VPP VIH Logic input voltage V DD = 5V 3.5 5.3 V VIL Logic input voltage -0.3 0.8 V IIH Logic input current V DD = 5V 0.05 0.5 µAV IN = VDD IIL Logic input current V DD = 5V -0.05 -0.5 µAV IN = 0.8V VOH Serial data out V DD = 5V 4.5 4.7 V I OUT = -200µA VOL Serial data out V DD = 5V 200 250 mV I OUT = 200µA fCLK Maximum clock frequency V DD = 5V 8.0 MHz T J = +25°C VDD = 5V 5.0 MHz T J = +125°C IDDQ Supply current V DD = 5V 100 300 µA All outputs high VDD = 5V 100 300 µA All outputs low IPPQ Supply current 10 100 µA Outputs high, no Load 10 100 µA Outputs low, no Load
Electrical Characteristics
DC Characteristics (Over recommended operating conditions, TA = 25°C, unless otherwise noted) Symbol Parameter Min Nom Max Units VDD Supply voltage 4.5 5.5 V VPP Supply voltage 20 80 V TJ Operating junction temperature -40 +125 °C Power-up sequence should be the following: 1. Connect ground. 2. Apply V DD. 3. Set all inputs (Data, CLK, etc.) to a known state. 4. Apply V PP. 5. The V PP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. Recommended Operating Conditions
Symbol Parameter Min Typ Max Units Conditions tPHL Blanking to output delay V DD = 5V 2000 ns C L = 30pF, 50% to 50% tPLH Blanking to output delay V DD = 5V 1000 ns C L = 30pF, 50% to 50% tf Output fall time V DD = 5V 1450 ns C L = 30pF, 90% to 10% tr Output rise time V DD = 5V 650 ns C L = 30pF, 10% to 90% tsu Data set-up time 75 ns See timing diagram th Data hold time 75 ns See timing diagram tpwd Minimum data pulse width 150 ns See timing diagram tpwclk Minimum clock pulse width 150 ns See timing diagram tcks Minimum time between clock activation 300 ns See timing diagram and strobe tpws Minimum strobe pulse width 100 ns See timing diagram tsto Typical time between strobe activation 500 ns See timing diagram and output transition AC Characteristics (TA = 25°C, over operating conditions unless otherwise noted) Input and Output Equivalent Circuits VDD Input GND VPP L/T GND HVOUT Logic Inputs GND Data Out Logic Data Output High Voltage Outputs VDD
Serial Clock Shift Register Contents Serial Strobe Latch Content Blanking Output Content Data Input Data Input HL to H H R 1 R2 ... RN-2 RN-1 RN-1 LL to H L R 1 R2 ... RN-2 RN-1 RN-1 XH to L R 1 R2 R3 ... RN-1 RN RN Note: L = Low Logic Level H = High Logic Level X = Irrelevant P= Present State R = Previous State Timing Diagram CLK Data In Strobe Blanking HVOUT tpwclk tpws tPHL tftr tPLH tsu 50% 50% 50% 90% 90% 10% 50% 10% th tpwd tcks tsto
2 Data Out
10 HV OUT13
11 HV OUT12
12 HV OUT11
13 Blank
14 GND
15 Clock
16 Strobe
18 HV OUT9
19 HV OUT8
20 HV OUT7
21 HV OUT6
22 HV OUT5
23 HV OUT4
24 HV OUT3
25 HV OUT2
26 HV OUT1
27 Data In
28-pin PLCC, 28-pin DIP, and SOW-28 25 19 24 23 22 21 20 5 116789 1 0 top view 28-pin PLCC top view 28-pin DIP and SOW-28 Package Outlines
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 11/12/01 ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.