HV5812P-G

HV5812_13 SUTEX | Alldatasheet

Document overview

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Technical content

Features

► HVCMOS® technology for high performance ► Operating voltage up to 80V ► High speed source driver ► 5.0V CMOS logic circuitry ► Up to 5.0MHz data input rate ► Excellent noise immunity ► Flexible high voltage supplies Functional Block Diagram 20-Channel, Serial-Input, Vacuum-Fluorescent Display Driver for Anode/Grid General Description The Supertex HV5812 is a 20-channel, serial input, vacuum- fluorescent display driver. It combines a 20-bit CMOS shift register, data latches, and control circuitry with high voltage MOSFET outputs. The HV5812 is primarily designed for vac- uum-fluorescent displays. The CMOS shift register and latches allow direct interfacing with microprocessor based systems. Data input rates are typi- cally over 5.0MHz with 5.0V logic supply. Especially useful for interdigit blanking, the BLANKING input disables the output source drives and turns on the sink drivers. Use with TTL may require external pull-up resistors to ensure an input logic high. BL STROBE DATA IN CLK DATA OUT 20-bit Shift Register 20-bit Latch VPP HVOUT1 HVOUT2 HVOUT3 HVOUT20GND VDD

Supertex inc. www.supertex.com Doc.# DSFP-HV5812 C072413 HV5812 Absolute Maximum Ratings Parameter Value Supply voltage, VDD -0.5V to +7.5V Supply voltage, VPP -0.5V to +90V Logic input levels -0.3V to VDD +0.3V Maximum junction temperature 125°C Storage temperature range -55°C to +150°C Power dissipation: 28-Lead PDIP 28-Lead PLCC 28-Lead SOW 2000mW 1900mW 1700mW Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to GND. Recommended Operating Conditions Sym Parameter Min Max Units VDD Supply voltage 4.5 5.5 V VPP Supply voltage 20 80 V Tj Operating junction temperature -40 +125 °C Pin Configuration Product Marking 28-Lead PLCC 1 28 4 26 28-Lead SOW YY = Year Sealed WW = Week Sealed L = Lot Number A = Assembler ID C = Country of Origin* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW AAA HV5812PJ LLLLLLLLLL CCCCCCCCCCC YY = Year Sealed WW = Week Sealed A = Assembler ID L = Lot Number C = Country of Origin* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW AAA HV5812WG LLLLLLLLLL CCCCCCCCCCC YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV5812P LLLLLLLLLL CCCCCCCCCCC AAA 28-Lead PDIP 28-Lead PLCC 28-Lead SOW 28-Lead PDIP 28 1 1 28 Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, etc.) to a known state. 4. Apply VPP. The VPP should not drop below VDD during operation. Power-down sequence should be the reverse of the above. Package may or may not include the following marks: Si or Package may or may not include the following marks: Si or Package may or may not include the following marks: Si or

Ordering Information

Part Number Package Packing HV5812P-G 28-Lead PDIP 13/Tube HV5812PJ-G 28-Lead PLCC 38/Tube HV5812PJ-G M904 28-Lead PLCC 500/Reel HV5812WG-G 28-LeadSOW 1000/Reel Typical Thermal Resistance Package θja 28-Lead PDIP 43OC/W 28-Lead PLCC 48OC/W 28-Lead SOW 55OC/W -G denotes a lead (Pb)-free / RoHS compliant package

Supertex inc. www.supertex.com Doc.# DSFP-HV5812 C072413 HV5812 Sym Parameter Min Typ Max Units Conditions IDSS Output leakage current - -5.0 -15 µA VOUT = 0V, TA = +70°C VOH High-level output HVOUT 78 78.5 - V IOUT = -25mA, VPP = 80V, Tj = +25°C 77 78 - IOUT = -25mA, VPP = 80V, Tj = +125°C DATA OUT 4.5 4.7 - V IOUT = -200µA, VDD = 5.0V VOL Low-level output HVOUT - 1.5 3.0 V IOUT = 1.0mA, Tj = +25°C, VDD = 5.0V - 2.3 4.0 IOUT = 1.0mA, Tj = +125°C, VDD = 5.0V DATA OUT - 200 250 V IOUT = +200µA, VDD = 5.0V ISINK Output pull-down current 2.0 3.5 - mA VOUT = 5.0V to VPP, VDD = 5.0V VIH High level logic input voltage 3.5 - 5.3 V VDD = 5.0V VIL Low level logic input voltage -0.3 - 0.8 V --- IIH High level logic input current - 0.05 0.5 µA VIN = VDD, VDD = 5.0V IIL Low level logic input current - -0.05 -0.5 µA VIN = 0.8V, VDD = 5.0V IDDQ Quiescent VDD supply current - 100 300 µA All outputs high, VDD = 5.0V - 100 300 All outputs low, VDD = 5.0V IPPQ Quiescent VPP supply current - 10 100 µA All outputs high, no load - 10 100 All outputs low, no load AC Characteristics (over recommended operating conditions, TA = 25OC, unless otherwise noted) tPHL Blanking to output delay - 2000 - ns CL = 30pF, 50% to 50%, VDD = 5.0V tPLH - 1000 - tf Output fall time - 1450 - ns CL = 30pF, 90% to 10%, VDD = 5.0V tr Output rise time - 650 - ns CL = 30pF, 10% to 90%, VDD = 5.0V tsu Data set-up time 75 - - ns See timing diagram th Data hold time 75 - - ns See timing diagram tpwd Minimum data pulse width 150 - - ns See timing diagram tpwclk Minimum clock pulse width 150 - - ns See timing diagram tcks Minimum time between clock activa- tion and strobe 300 - - ns See timing diagram tpws Minimum strobe pulse width 100 - ns See timing diagram tsto Typical time between strobe activa- tion and output transition - 500 - ns See timing diagram fCLK Maximum clock frequency - 8.0 - MHz Tj = +25°C, VDD = 5.0V

Electrical Characteristics

DC Characteristics (over recommended operating conditions, TA = 25OC, unless otherwise noted)

Supertex inc. www.supertex.com Doc.# DSFP-HV5812 C072413 HV5812 Function Table Timing Diagram Serial Data Input Clock Input Shift Register Contents Serial Data Output Strobe Input Latch Content Blanking Output Content H L to H H R1 R2 ... RN-2 RN-1 RN-1 - - - - - - - - - - L L to H L R1 R2 ... RN-2 RN-1 RN-1 - - - - - - - - - - X H to L R1 R2 R3 ... RN-1 RN RN - - - - - - - - - - Note: L = Low logic level H = High logic level X = Irrelevant P = Present state R = Previous state CLK DATA IN STROBE BL HVOUT tPWCLK tPWS tPHL tf tr tPLH tSU 50% 90% 10% 50% 10% th tPWD tCKS tSTO 90% 50% 50% 50% 50% 50% 50% VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL 50% 50% Input and Output Equivalent Circuits VDD INPUT GND VPP L/T GND HVOUT Logic Inputs GND Data Out Logic Data Output High Voltage Outputs VDD

Supertex inc. www.supertex.com Doc.# DSFP-HV5812 C072413 HV5812 28-Lead PDIP Pin Description Pin # Function

1 VPP

2 Data Out

3 HVOUT20

4 HVOUT19

5 HVOUT18

6 HVOUT17

7 HVOUT16

8 HVOUT15

9 HVOUT14

10 HVOUT13

Pin # Function

11 HVOUT12

12 HVOUT11

13 BLANKING

14 GND

15 CLOCK

16 STROBE

17 HVOUT10

18 HVOUT9

19 HVOUT8

20 HVOUT7

Pin # Function

21 HVOUT6

22 HVOUT5

23 HVOUT4

24 HVOUT3

25 HVOUT2

26 HVOUT1

27 Data In

28 VDD

28-Lead SOW Pin Description Pin # Function Pin # Function Pin # Function 28-Lead PLCC Pin Description Pin # Function Pin # Function Pin # Function

Supertex inc. www.supertex.com Doc.# DSFP-HV5812 C072413 HV5812 28-Lead PDIP (.600in Row Spacing) Package Outline (P) 1.565x.580in body, .250in height (max), .100in pitch Note 1 (Index Area) D A A2 Seating Plane E A A Side View Top View View B e View A - A eA b View B L eB Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol A A1 A2 b b1 D D1 E E1 e eA eB L Dimension (inches) .100 BSC .600 BSC .600* .115 JEDEC Registration MS-011, Variation AB, Issue B, June, 1988. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-28DIPP, Version B041009.

Supertex inc. www.supertex.com Doc.# DSFP-HV5812 C072413 HV5812 28-Lead PLCC Package Outline (PJ) Symbol A A1 A2 b b1 D D1 E E1 e R Dimension (inches) .050 BSC .025 JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale. Supertex Doc. #: DSPD-28PLCCPJ, Version B031111. .150max .048/.042 x 45O .075max D E Top View View B A A2A1 Seating Plane Note 1 (Index Area) .056/.042 x 45O Base Plane .020min b View B Horizontal Side View Vertical Side View Note 2 .020max (3 Places) R e 4 26281 Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary.

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com HV5812 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to: http://www.supertex.com/packaging.html.) Doc.# DSFP-HV5812 C072413 28-Lead SOW (Wide Body) Package Outline (WG) 17.90x7.50mm body, 2.65mm height (max), 1.27mm pitch Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1 Dimension (mm) 1.27 BSC 0.25 0.40 1.40 REF 0.25 BSC 0O 5O JEDEC Registration MS-013, Variation AE, Issue E, Sep. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-28SOWWG, Version D041309. EE1 D e b A A2 Seating Plane A A Top View Side View Note 1 (Index Area 0.25D x 0.75E1) View B View A-A Seating Plane Gauge Plane L View B θ h h Note 1 Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.