HV57708_07 SUTEX | Alldatasheet
Document overview
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Technical content
Features
HVCMOS® technology 5.0V CMS Logic Output voltage up to +80V Low power level shifting 32MHz equivalent data rate Latched data outputs Foreward and reverse shifting options (DIR pin) Diode to V PP allows effi cient power recovery Outputs may be hot switched Functional Block Diagram 32MHz, 64-Channel Serial to Parallel Converter with Push-Pull Outputs General Description The device has 4 parallel 16-bit registers, permitting data rates 4x the speed of one (they are clocked together). There are also 64 latches and control logic to perform the polarity select and blanking of the outputs. HVOUT1 is connected to the fi rst stage of the fi rst shift register through the polarity and blanking logic. Data is shifted through the shift registers on the logic low to high transition of the clock. The DIR pin causes CCW shifting when connected to GND, and CW shifting when connected to VDD. A data output buffer is provided for cascading devices. This output refl ects the current status of the last bit of the shift register (HVOUT64). Operation of the shift register is not affected by the LE (latch enable), BL (blanking), or the POL (polarity) inputs. Transfer of data from the shift registers to the latches occurs when the LE input is high. The data in the latches is stored when the LE is low. HV 3 HV 63 HV 4 HV 64 HV 2 HV 62 HV 1 HV 61 POL PPV OUT BLD 4 OUT OUT OUT OUT OUT OUT OUT LEI D 4O SR4 SR3 SR2 SR1 CLK DIR GND DDV D 3O D 2O D 1O D 3I D 2I D 1I D 1O D 2O D 3O D 4O D 1I D 2I D 3I D 4I Note: Each SR (shift register) provides 16 outputs. SR1 supplies every fourth output starting with 1; SR2 supplies every fourth output with 2, etc. General Description The HV57708 is a low voltage serial to high voltage parallel converter with push-pull outputs. The device has been designed for use as a driver for EL displays. It can also be used in any application requiring multiple output high voltage current sourcing and sinking capability such as driving plasma panels, vacuum fl uorescent displays, or large matrix LCD displays.
Ordering Information
-G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value Supply voltage, VDD -0.5V to +7.5V Output voltage , VPP -0.5V to +90V Logic input levels -0.3V to V DD + 0.3V Ground current(1) 1.5A Continuous total power dissipation(2) 1200mW Operating temperature range -40°C to +85°C Storage temperature range -65°C to +150°C Lead temperature 1.6mm from case for 10 seconds 260°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. Limited by the total dissipated in the package. 2. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C. Recommended Operating Conditions Symbol Parameter Min Max Units VDD Logic supply voltage 4.5 5.5 V VPP Output voltage 8.0 80 V VIH High-level input voltage V DD - 0.5V - V VIL Low-level input voltage 0 0.5 V fCLK Clock frequency per register - 8.0 MHz TA Operating free-air temperature -40 +85 °C Notes: Power-up sequence should be the following*: 1. Apply ground 2. Apply V DD 3. Set all inputs (DIN, CLK, LE , POL, etc.) to a known state 4. Apply VPP 5. The VPP should not drop below VDD or fl oat during operation Power-down sequence should be the reverse of the above Pin Confi guration 80-Lead PQFP (PG) (top view) YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV57708PG LLLLLLLLLL CCCCCCCC AAA Product Marking 80-Lead PQFP (PG)
Symbol Parameter Min Max Units Conditions IDD VDD supply current - 15 mA V DD = VDD max, fCLK = 8MHz IPP High voltage supply current - 100 µA Outputs high - 100 µA Outputs low IDDQ Quiescent VDD supply current - 100 µA All V IN = VDD VOH High level output HVOUT 65 - V I O = -15mA, VPP = +80V DOUT VDD - 0.5V - V I O = -100µA VOL Low level output HVOUT - 7.0 V I O = 12mA, VPP = +80V DOUT - 0.5 V I O = 100µA IIH High-level logic input current - 1.0 µA V IH = VDD IIL Low-level logic input current - -1.0 µA V IL = 0V VOC High voltage clamp diode - 1.0 V I OC = 1.0mA Symbol Parameter Min Max Units Conditions fCLK Clock frequency - 8 MHz Per register tWL, tWH Clock width high or low 62 - ns --- tSU Data set-up time before clock rises 10 - ns --- tH Data hold time after clock rises 15 - ns --- tON, tOFF Time from latch enable to HVOUT - 500 ns C L = 15pF tDHL Delay time clock to data high to low - 70 ns C L = 15pF tDLH Delay time clock to data low to high - 70 ns C L = 15pF tDLE* Delay time clock to LE low to high 25 - ns --- tWLE LE pulse width 25 - ns --- tSLE LE set-up time before clock rises 0 - ns --- * tDLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize).
Input and Output Equivalent Circuits Switching Waveforms VDD Input GND VPP GND HVOUT Logic Inputs GND Data Out Logic Data Output High Voltage Outputs V DD Latch Enable HVOUT w/ S/R LOW Data Valid50% 50%Data Input Clock Data Out 50% 50% 50% tSU tH tWL tWH 50% tDLH tDHL 50% tWLEtDLE tSLE 50% 50% tON 10% HVOUT w/ S/R HIGH 90% 90%10% tOFF VIH VIL VIH VIL VOH VOL VOH VOL VIH VOL VOH VOL VOH VOL 10% 90% 90% 10% 50% tf tr
DIR = H DIR = L DIR = H; CW (HVOUT1 → HVOUT64) DIR = L; CCW (HVOUT64 → HVOUT1) HV OUT 32 HV OUT2 HV OUT1 HOUT33 HOUT63 HOUT64 Pin SR1 SR2 SR3 SR4 Function Table Function Inputs Outputs Data CLK LE BL POL DIR Shift Reg HV Outputs Data Out All O/P high X X X L L X - H - All O/P low X X X L H X - L- O/P normal X X X H H X - No inversion - O/P inverted X X X H L X - Inversion - Data falls through (latches transparent) L_ ↑ _ HHHX L L - H_ ↑ _ HHHX H H - L_ ↑ _ HHLX L H - H_ ↑ _ HHLX H L - Data stored/ latches loaded X X L H H X * Stored Data - XX L H L X * Inversion of stored data - I/O relation DI/O1-4A _↑ _ HHHH Q n→Qn+1 New H or L D I/O1-4B DI/O1-4A _↑ _ LHHH Q n→Qn+1 Previous H or L D I/O1-4B DI/O1-4B _↑ _ LHHL Q n→Qn-1 Previous H or L D I/O1-4A DI/O1-4B _↑ _ HHHL Q n→Qn-1 New H or L D I/O1-4A Note: * = data at the last CLK ↑ Shift Register Operation
# Function
1 HVOUT24/41
2 HVOUT23/42
3 HVOUT22/43
4 HVOUT21/44
5 HVOUT20/45
6 HVOUT29/46
7 HVOUT18/47
8 HVOUT17/48
9 HVOUT16/49
10 HVOUT15/50
11 HVOUT14/51
12 HVOUT13/52
13 HVOUT12/53
14 HVOUT11/54
15 HVOUT10/55
16 HVOUT9/56
17 HVOUT8/57
18 HVOUT7/58
19 HVOUT6/59
20 HVOUT5/60
# Function
21 HVOUT4/61
22 HVOUT3/62
23 HVOUT2/63
24 HVOUT1/64
25 DIN1/DOUT4(A)
26 DIN2/DOUT3(A)
27 DIN3/DOUT2(A)
28 DIN4/DOUT1(A)
30 CLK
32 VDD
33 DIR
34 GND
35 POL
36 DOUT4/DIN1(B)
37 DOUT3/DIN2(B)
37 DOUT2/DIN3(B)
39 DOUT1/DIN4(B)
40 VPP
# Function
41 HVOUT64/1
42 HVOUT63/2
43 HVOUT62/3
44 HVOUT61/4
45 HVOUT60/5
46 HVOUT59/6
47 HVOUT58/7
48 HVOUT57/8
49 HVOUT56/9
50 HVOUT55/10
51 HVOUT54/11
52 HVOUT53/12
53 HVOUT52/13
54 HVOUT51/14
55 HVOUT50/15
56 HVOUT49/16
57 HVOUT48/17
58 HVOUT47/18
59 HVOUT46/19
60 HVOUT45/20
# Function
61 HVOUT44/21
62 HVOUT43/22
63 HVOUT42/23
64 HVOUT41/24
65 HVOUT40/25
66 HVOUT39/26
67 HVOUT38/27
68 HVOUT37/28
69 HVOUT36/29
70 HVOUT35/30
71 HVOUT34/31
72 HVOUT33/32
73 HVOUT32/33
74 HVOUT31/34
75 HVOUT30/35
76 HVOUT29/36
77 HVOUT28/37
78 HVOUT27/38
79 HVOUT26/39
80 HVOUT25/40
Note: Pin designation for DIR = H/L. Example: For DIR = H, pin 41 is HVOUT64. For DIR = L, pin 41 is HVOUT1. For CW/CCW Shift see function table Q N → QN+1.
(The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV57708 A083107 80-Lead PQFP Package Outline (PG) 20x14mm body, 0.80mm pitch Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ θ1 Dimension (mm) 0.80 BSC 0.73 1.95 REF 0.25 BSC 0O 5O JEDEC Registration MO-112, Variation CB-1, Issue B, Sept.1995. Drawings not to scale. Note 1: A Pin 1 identifi er must be located in the index area indicated. The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature. Seating Plane Gauge Plane θL View BView B be Side View A2A E D Seating Plane Top View Note 1 (Index Area D1/4 x E1/4)