HV57708 SUTEX | Alldatasheet
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Features
❏ Processed with HVCMOS® technology ❏ 5V CMOS logic ❏ Output voltages up to 80V ❏ Low power level shifting ❏ 32MHz equivalent data rate ❏ Latched data outputs ❏ Forward and reverse shifting options (DIR pin) ❏ Diode to VPP allows efficient power recovery ❏ Outputs may be hot switched ❏ Hi-Rel processing available Absolute Maximum Ratings Supply voltage, VDD 1 -0.5V to +7.5V Output voltage, VPP 1 -0.5V to +90V Logic input levels1 -0.3V to VDD +0.3V Ground current 2 1.5A Continuous total power dissipation 3 Plastic 1200mW Ceramic 1900mW Operating temperature range Plastic -40 to 85 °C Ceramic -55 °C to 125°C Storage temperature range -65 °C to +150°C Lead temperature 1.6mm (1/16 inch) 260 °C from case for 10 seconds Notes: 1. All voltages are referenced to GND. 2. Limited by the total power dissipated in the package. 3. For operation above 25 °C ambient derate linearly to maximum operating temperature at 20mW/°C for plastic and at 19mW/°C for ceramic. For detailed circuit and application information, please refer to application note AN-H3.
Symbol Parameter Min Max Units VDD Logic supply voltage 4.5 5.5 V VPP Output voltage 8 80 V VIH High-level input voltage V DD -0.5V V VIL Low-level input voltage 0 0.5 V fCLK Clock frequency per register 8 MHz TA Operating free-air temperature Plastic -40 +85 °CCeramic -55 +125 Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply V DD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply V PP. 5. The V PP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. Electrical Characteristics (over recommended operating conditions unless noted, TA=-40°C to +85°C) DC Characteristics Symbol Parameter Min Max Units Conditions IDD VDD supply current 15 mA V DD = VDD max fCLK = 8MHz IPP High voltage supply current 100 µA Outputs high 100 µA Outputs low IDDQ Quiescent VDD supply current 100 µA All VIN = VDD VOH High-level output HV OUT 65 V I O= -15mA, VPP = 80V Data out V DD - 0.5 V I O= -100µA VOL Low-level output HV OUT 7V I O = 12mA, VPP = 80V Data out 0.5 V I O= 100µA IIH High-level logic input current 1 µAV IH = VDD IIL Low-level logic input current -1 µAV IL = 0V VOC High voltage clamp diode 1 V I OC = 1mA Recommended Operating Conditions AC Characteristics (TA = 85°C max. Logic signal inputs and Data inputs have tr, tf ≤ 5ns [10% and 90% points]) Symbol Parameter Min Max Units Conditions fCLK Clock frequency 8 MHz Per Register tWL,tWH Clock width high or low 62 ns tSU Data set-up time before clock rises 10 ns tH Data hold time after clock rises 15 ns tON, tOFF Time from latch enable to HVOUT 500 ns C L = 15pF tDHL Delay time clock to data high to low 70 ns C L = 15pF tDLH Delay time clock to data low to high 70 ns C L = 15pF tDLE* Delay time clock to LE low to high 25 ns tWLE Width of LE pulse 25 ns tSLE LE set-up time before clock rises 0 ns * tDLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize). HV57708
Data Valid50% 50%Data Input Clock Data Out 50% 50% 50% tSU tH tWL tWH 50% tDLH tDHL 50% tWLEtDLE tSLE 50% 50% tON 10% HVOUT w/ S/R HIGH 90% 90%10% tOFF VIH VIL VIH VIL VOH VOL VOH VOL VIH VOL VOH VOL VOH VOL 10% 90% 90% 10% 50% tf tr VDD Input GND VPP GND HVOUT Logic Inputs GND Data Out Logic Data Output High Voltage Outputs VDD Input and Output Equivalent Circuits Switching Waveforms
Function Shift Reg HV Outputs Data Out All O/P High X X X L L X H All O/P Low X X X L H X L O/P Normal X X X H H X No inversion O/P Inverted X X X H L X Inversion L HHHX L L H HHHX H H LH H L X L H HH H L X H L Data Stored/ XX LH HX * Stored Data Latches Loaded XX LH LX * Inversion of Stored Data D I/O1-4A H H H H Q n→ Qn +1 New H or L D I/O1 – 4B DI/O1-4A L H H H Q n→ Qn +1 Previous D I/O1 – 4B H or L DI/O1-4B L H H L Q n→ Qn -1 Previous D I/O1 – 4A H or L DI/O1-4B H H H L Q n→ Qn -1 New H or L D I/O1 – 4A Data CLK LE BL POL DIR Note: * = dependent on previous stage’s state. See Pin configuration for DIN and DOUT pin designation for CW and CCW shift. Function Table I/O Relation Note: Each SR (shift register) provides 16 outputs. SR1 supplies every fourth output starting with 1; SR2 supplies every fourth output with 2, etc. ↑Data Falls Through (Latches Transparent)
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 02/06//02 ©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. HV57708 1 24 4164 Index top view 80-pin Gullwing Package 25 26 27 28 36 37 38 39 DIR = H DIR = L DIR = H; CW (HVOUT1 → HVOUT64) DIR = L; CCW (HVOUT64 → HVOUT1) HVOUT32 HV OUT2 HVOUT1 HOUT33 H OUT63 HOUT64 Pin SR1 SR2 SR3 SR4 Pin Configurations HV577 80-pin Gullwing Pin Function 1H V OUT 24/41 2H V OUT 23/42 3H V OUT 22/43 4H V OUT 21/44 5H V OUT 20/45 6H V OUT 19/46 7H V OUT 18/47 8H V OUT 17/48 9H V OUT 16/49
10 HV OUT 15/50
11 HV OUT 14/51
12 HV OUT 13/52
13 HV OUT 12/53
14 HV OUT 11/54
15 HV OUT 10/55
16 HV OUT 9/56
17 HV OUT 8/57
18 HV OUT 7/58
19 HV OUT 6/59
20 HV OUT 5/60
21 HV OUT 4/61
22 HV OUT 3/62
23 HV OUT 2/63
24 HV OUT 1/64
25 D IN 1/DOUT 4(A)
26 D IN 2/DOUT 3(A)
27 D IN 3/DOUT 2(A)
28 D IN 4/DOUT 1(A)
30 CLK
33 DIR
34 GND
35 POL
OUT 4/DIN 1(B)
37 D OUT 3/DIN 2(B)
38 D OUT 2/DIN 3(B)
39 D OUT 1/DIN 4(B)
40 V PP
Note: Pin designation for DIR = H/L. Example: For DIR = H, pin 41 is HV OUT 64. For DIR = L, pin 41 is HVOUT 1. For CW/CCW Shift see function table QN → QN+1.