HV57009 SUTEX | Alldatasheet
Document overview
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Technical content
Features
❏ Processed with HVCMOS ® technology ❏ 5V CMOS Logic ❏ Output voltage up to -85V ❏ Output current source control ❏ 16MHz equivalent data rate ❏ Latched data outputs ❏ Forward and reverse shifting options (DIR pin) ❏ Diode to VDD allows efficient power recovery ❏ Hi-Rel processing available Package Options Device 80-Lead Quad Ceramic Gullwing
80 Lead Quad
(MIL-Std-833 Processed*) HV57009 HV57009DG HV57009PG HV57009X RBHV57009DG * For Hi-Rel process flows, refer to page 5-3 of the Databook.
Ordering Information
Symbol Parameter Min Max Units Conditions IDD VDD supply current 15 mA V DD = VDD, max fCLK = 8MHz INN High voltage supply current -10 µA Outputs off, HVOUT = -85V (total of all outputs) IDDQ Quiescent VDD supply current 100 µA All inputs = VDD, except +IN = VSS = GND VOH High-level output Data out V DD -0.5 V I O = -100µA HVOUT +1 V DD VI O = -2mA VOL Low-level output Data out +0.5 V I O = 100µA IIH High-level logic input current 1 µAV IH = VDD IIL Low-level logic input current -1 µAV IL = 0V ICS HV output source current -2 mA V REF = 2V, REXT = 1K, see Figures 8a and 8b -0.1 mA V REF = 0.1V, REXT = 1K, see Figure 8a and 8b ∆ICS HV output source current for IREF = 2.0mA 10 % V REF = 2V, REXT = 1K
Electrical Characteristics
DC Characteristics (All voltages are referenced to VSS, VSS = 0, TA = 25°C) Symbol Parameter Min Max Units Conditions fCLK Clock frequency DC 8 MHz Per register tWL, tWH Clock width high or low 62 ns tSU Data set-up time before clock rises 10 ns tH Data hold time after clock rises 15 ns tON, tOFF Time for latch enable to HVOUT 500 ns C L = 15pF tDHL Delay time clock to data high to low 70 ns C L = 15pF tDLH Delay time clock to data low to high 70 ns C L = 15pF tDLE Delay time clock to LE low to high 25 ns tWLE Width of LE pulse 25 ns tSLE LE set-up time before clock rises 0 ns tr, tf Maximum allowable clock rise and fall time 100 ns (10% and 90% points) AC Characteristics (Logic signal inputs and Data inputs have tr, tf ≤ 5ns [10% and 90% points] for measurements) Notes 1: Current going out of the chip is considered negative. HV57009
Symbol Parameter Min Max Units VDD Logic supply voltage 4.5 5.5 V HVOUT HV output off voltage -85 V DD V VIH High-level input voltage V DD - 1.2V V DD V VIL Low-level input voltage 0 1.2 V fCLK Clock frequency per register DC 8 MHz TA Operating free-air temperature Plastic -40 +85 °C Ceramic -55 +125 °C Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply V DD. 3. Set all inputs to a known state. Power-down sequence should be the reverse of the above. Recommended Operating Conditions Figure 1: Input and Output Equivalent Circuits
Previous IO = IREF Previous IO = 0 IO = 0 IO = IREF Data Valid50% 50%Data Input CLK Data Out 50% 50% 50% tSU tH tWL tWH 50% tDLH tDHL 50% tWLEtDLE tSLE 50% 50% tON 10% HVOUT w/ data input HIGH 90% 90%10% tOFF VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD HVOUT (off) VDD HVOUT (off) 10% 90% 90% 10% 50% tf tr Figure 2: Switching Waveforms
DIR = VDD; CW (HVOUT1→HVOUT64) DIR = VSS; CCW (HVOUT64→HVOUT1) →CW →CW Pin Function 1H V OUT 24 2H V OUT 23 3H V OUT 22 4H V OUT 21 5H V OUT 20 6H V OUT 19 7H V OUT 18 8H V OUT 17 9H V OUT 16
10 HV OUT 15
11 HV OUT 14
12 HV OUT 13
13 HV OUT 12
14 HV OUT 11
15 HV OUT 10
16 HV OUT 9
17 HV OUT 8
18 HV OUT 7
19 HV OUT 6
20 HV OUT 5
21 HV OUT 4
22 HV OUT 3
23 HV OUT 2
24 HV OUT 1
25 D I/O1A
26 D I/O2A
27 N/C
28 N/C
30 CLK
33 DIR
36 D I/O2B
37 D I/O1B
38 N/C
40 V BP
Figure 5: Pin Configurations 80-pin Gullwing Package Pin Function
41 HV OUT 64
42 HV OUT 63
43 HV OUT 62
44 HV OUT 61
45 HV OUT 60
46 HV OUT 59
47 HV OUT 58
48 HV OUT 57
49 HV OUT 56
50 HV OUT 55
51 HV OUT 54
52 HV OUT 53
53 HV OUT 52
54 HV OUT 51
55 HV OUT 50
56 HV OUT 49
57 HV OUT 48
58 HV OUT 47
59 HV OUT 46
60 HV OUT 45
61 HV OUT 44
62 HV OUT 43
63 HV OUT 42
64 HV OUT 41
65 HV OUT 40
66 HV OUT 39
67 HV OUT 38
68 HV OUT 37
69 HV OUT 36
70 HV OUT 35
71 HV OUT 34
72 HV OUT 33
73 HV OUT 32
74 HV OUT 31
75 HV OUT 30
76 HV OUT 29
77 HV OUT 28
78 HV OUT 27
79 HV OUT 26
80 HV OUT 25
Figure 6: Package Outline Figure 7: Shift Register Operation Notes: 1. Pin designation for DIR = V DD. 2. A 0.1 µF capacitor is needed between VDD and VBP (pin 40) for better output current stability and to prevent transient cross-coupling between outputs. See Fig. 8a and 8b. DIR = VDD:D I/O1A D I/O2A D I/O2B D I/O1B DIR = VSS:D I/O2A D I/O1A D I/O1B D I/O2B
+IN -IN RD* 10K CD* 390pF HV570 Logic To other outputs - + 0.1µF VBP VSS VREF IOUT HVOUT VDD0.1µF VBP IREF REXT +IN -IN RD* 10K CD* 390pF HV570 Logic To other outputs VSS Since IOUT = IREF = Therefore, if IOUT = 2mA and VREF = -5V → REXT = 2.5KΩ. If IOUT = 1mA and REXT = 1KΩ → VREF = -1V. If R EXT >10KΩ, add series network R D and C D to ground for stability as shown. This control method behaves linearly as long as the operational amplifier is not saturated. However, it requires a negative power source and needs to provide a current I REF = IOUT for each HV570 chip being controlled. If HVOUT ≥ +1V, the HVOUT cascode may no longer operate as a perfect current source, and the output current will diminish. This effect depends on the magnitude of the output current. Given IOUT and VREF, the REXT can be calculated by using: REXT = VREF = VREF IREF IOUT The intersection of a set of I OUT and VREF values can be located in the graph shown below. The value picked for REXT must always be in the shaded area for linear operation. This control method has the advantage that V REF is positive, and draws only leakage current. If REXT > 10K, add series network RD and CD to ground for stability as shown. Note: Lower reference current I REF, results in higher distortion, ∆ICS, on the output. *Required if REXT > 10K or REXT is replaced by a constant current source. Typical Current Programming Circuits Figure 8b: Positive Control Figure 8a: Negative Control VREF REXT 12345 IOUT (mA) VREF (V) 100 250 500 REXT = 1K
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