HV5630_13 SUTEX | Alldatasheet
Document overview
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Technical content
Features
► Processed with HVCMOS® technology ► Sink current minimum 100mA ► Shift register speed 8.0MHz ► Polarity and Blanking inputs ► CMOS compatible inputs ► Forward and reverse shifting options ► Diode to VPP allows efficient power recovery
Supertex inc. www.supertex.com Doc.# DSFP-HV5630 C072313 HV5630 Absolute Maximum Ratings Supply voltage, VDD 1 -0.5V to +15V Output voltage, VPP 1 -0.5V to +315V Logic input levels1 -0.5V to VDD +0.5V Ground current2 1.5A Continuous total power dissipation3 1200mW Operating temperature range -40OC to +85OC Storage temperature range -65OC to +150OC Parameter Value Symbol Parameter Min Max Units Conditions Recommended Operating Conditions VDD Logic voltage supply 10.8 13.2 V --- HVOUT High voltage output -0.3 +300 V --- VIH Input high voltage VDD -2.0 VDD V --- VIL Input low voltage 0 2.0 V --- fCLK Clock frequency - 8.0 MHz --- TA Operating free-air temperature -40 +85 OC --- Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. All voltages are referenced to VSS 2. Duty cycle is limited by the total power dissipated in the package 3. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C. Power-Up Sequence Power-up sequence should be the following: 1. Connect ground 2. Apply VDD 3. Set all inputs to a known state Power-down sequence should be the reverse of the above. Pin Configuration 1 44 6 40 YY = Year Sealed WW = Week Sealed L = Lot Number A = Assembler ID C = Country of Origin* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW AAA HV5630PJ LLLLLLLLLL CCCCCCCCCCC 44-Lead PLCC (top view) Product Marking 44-Lead PLCC Package may or may not include the following marks: Si or
Ordering Information
Part Number Package Packing HV5630PJ-G 44-Lead PLCC 27/Tube HV5630PJ-G M903 44-Lead PLCC 500/Reel Typical Thermal Resistance Package θja 44-Lead PLCC 37OC/W -G denotes a lead (Pb)-free / RoHS compliant package
Supertex inc. www.supertex.com Doc.# DSFP-HV5630 C072313 HV5630 Sym Parameter Min Max Units Conditions Electrical Characteristics (over recommended operating conditions unless otherwise noted) DC Characteristics AC Characteristics (VDD = 12V, TC = 25OC) Sym Parameter Min Max Units Conditions fCLK Clock frequency - 8.0 MHz --- tW Clock width, high or low 62 - ns --- tSU Data set-up time before CLK falls 25 - ns --- tH Data hold time after CLK falls 10 - ns --- tON Turn-on time, HVOUT from enable - 500 ns RL = 2.0KΩ to VPP max. tDHL Delay time clock to data high to low - 100 ns CL = 15pF tDLH Delay time clock to data low to high - 100 ns CL = 15pF tDLE Delay time clock to LE low to high 50 - ns --- tWLE Width of LE pulse 50 - ns --- tSLE LE setup time before clock falls 50 - ns --- IDD VDD supply current - 15 mA fCLK = 8.0MHz, FDATA = 4.0MHz IDDQ VDD supply current (quiescent) - 100 µA VIN = 0V IO(OFF) Off state output current - 10 µA All outputs high, all SWS parallel IIH High-level logic input current - 1.0 µA VIH = VDD IIL Low-level logic input current - -1.0 µA VIL = 0V VOH High-level output data out VDD -1.0V - V IDOUT = -100µA VOL Low-level output voltage HVOUT - 15 V IHVOUT = +100mA DATA OUT - 1.0 V IDOUT = +100µA VOC HVOUT clamp voltage - -1.5 V IOL = -100mA Input and Output Equivalent Circuits VDD DATA IN HVOUT Logic Inputs DATA OUT Logic Data Output High Voltage Outputs VDD HVIN VSS VSS VSS
Supertex inc. www.supertex.com Doc.# DSFP-HV5630 C072313 HV5630 Switching Waveforms LE HVOUT w/ S/R HIGH Data Valid 50% 50% DATA IN CLK DATA OUT 50% 50% 50% tSU tH tWH tWL 50% 50% tDLH tDHL 50% tWLE tDLE tSLE 50% 50% 10% tON VIH VIL VIH VIL VOH VOL VOH VOL VIH VIL VOH VOL Functional Table Function Inputs Outputs Data CLK LE BL POL Shift Reg HV Outputs Data Out Load latches Transparent latch mode Notes: H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transistion. * dependent on previous stage’s state before the last CLK ↓ or last LE high.
Supertex inc. www.supertex.com Doc.# DSFP-HV5630 C072313 HV5630 44-Lead PLCC Pin Description Pin Function Description
1 HVOUT17
High voltage outputs.
2 HVOUT16
3 HVOUT15
4 HVOUT14
5 HVOUT13
6 HVOUT12
7 HVOUT11
8 HVOUT10
9 HVOUT9
10 HVOUT8
11 HVOUT7
12 HVOUT6
13 HVOUT5
14 HVOUT4
15 HVOUT3
16 HVOUT2
17 HVOUT1
18 DATA OUT Data output pin.
19 N/C
No internal connection.20 N/C
21 N/C
22 POL Inverts the polarity of the HVOUT pins
23 CLK Clock pin, shift registers shift data on falling edge of input clock. 24 VSS Reference voltage, usually ground. 25 VDD Logic supply voltage. 26 LE Latch enable pin, data is shifted from shift register to latches on logic input high. 27 DATA IN Data input pin. 28 BL Blanking pin sets all HVOUT pins low or high depending upon state of polarity. See function table. 29 N/C No internal connection.
30 HVOUT32
High voltage outputs.
31 HVOUT31
32 HVOUT30
33 HVOUT29
34 HVOUT28
35 HVOUT27
36 HVOUT26
37 HVOUT25
38 HVOUT24
39 HVOUT23
40 HVOUT22
41 HVOUT21
42 HVOUT20
43 HVOUT19
44 HVOUT18
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888 www.supertex.com (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV5630 C072313 HV5630 44-Lead PLCC Package Outline (PJ) .653x.653in body, .180in height (max), .050in pitch Symbol A A1 A2 b b1 D D1 E E1 e R Dimension (inches) .050 BSC .025 JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-44PLCCPJ, Version F031111. 164 044 .150max .048/.042 x 45O D E Top View View B A A2A1 Seating Plane .056/.042 x 45O Base Plane .020min b View B Horizontal Side View Vertical Side View .020max (3 Places) R e Note 1 (Index Area) Note 2 .075max Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary.