HV5622X

HV5522_07 SUTEX | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 8

Technical content

Features

❏ Processed with HVCMOS® technology ❏ Sink current minimum 100mA ❏ Shift register speed 8MHz ❏ Polarity and Blanking inputs ❏ CMOS compatible inputs ❏ Forward and reverse shifting options ❏ Diode to VPP allows efficient power recovery ❏ 44-lead ceramic surface mount package ❏ Hi-Rel processing available HV5522/HV5530 HV5622/HV5630

Electrical Characteristics (over recommended operating conditions unless noted) DC Characteristics Symbol Parameter Min Max Units Conditions IDD VDD supply current 15 mA f CLK = 8MHz FDATA = 4MHz IDDQ Quiescent VDD supply current 100 µAV IN = 0V IO(OFF) Off state output current 10 µA All outputs high All SWS parallel IIH High-level logic input current 1 µAV IH = VDD IIL Low-level logic input current -1 µAV IL = 0V VOH High-level output data out V DD - 1.0V V I Dout = -100µA HVOUT 15.0 V I HVout = +100mA Data out 1.0 V I Dout = +100µA VOC HVOUT clamp voltage -1.5 V I OL = -100mA VOL Low-level output voltage AC Characteristics (VDD = 12V, TC = 25°C) Symbol Parameter Min Max Units Conditions fCLK Clock frequency 8 MHz tW Clock width high or low 62 ns tSU Data set-up time before clock falls 25 ns tH Data hold time after clock falls 10 ns tON Turn on time, HVOUT from enable 500 ns R L = 2KΩ to VPP MAX tDHL Delay time clock to data high to low 100 ns C L = 15pF tDLH Delay time clock to data low to high 100 ns C L = 15pF tDLE Delay time clock to LE low to high 50 ns tWLE Width of LE pulse 50 ns tSLE LE set-up time before clock falls 50 ns Recommended Operating Conditions Symbol Parameter Min Max Units VDD Logic supply voltage 10.8 13.2 V HV5530 and HV5630 -0.3 +300 V HV5522 and HV5622 -0.3 +220 V VIH High-level input voltage V DD - 2V V DD V VIL Low-level input voltage 0 2.0 V fCLK Clock frequency 8 MHz Plastic -40 +85 °C Ceramic -55 +125 °C Note: Power-up sequence should be the following: 1. Connect ground. 2. Apply V DD. 3. Set all inputs to a known state. Power-down sequence should be the reverse of the above. HVOUT High voltage output TA Operating free-air temperature HV5522/HV5530/HV5622/HV5630

HV5522/HV5530/HV5622/HV5630 Latch Enable HVOUT w/ S/R HIGH Data Valid50% 50%Data Input Clock Data Out 50% 50% 50% tSU tH tWH tWL 50% 50% tDLH tDHL 50% tWLEtDLE tSLE 50% 50% 10% tON VIH VIL VIH VIL VOH VOL VOH VOL VIH VIL VOH VOL Input and Output Equivalent Circuits Switching Waveforms VDD Input HVOUT Logic Inputs Data Out Logic Data Output High Voltage Outputs VDD HVIN VSS VSS VSS

HV5522/HV5530/HV5622/HV5630 Functional Block Diagram Function Table Inputs Outputs Function Shift Reg HV Outputs Data Out 12 … 32 1 2 … 32 * All on X X X L L * * … *O n O n … On * All off X X X L H * * … * Off Off … Off * Notes: H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transistion. * = dependent on previous stage’s state before the last CLK ↓ or last LE high. Data CLK LE BL POL Transparent Latch mode Load Latches Polarity Blanking Latch Enable Data Input Clock Data Out 32-Bit Shift Register HVOUT1 (Outputs 3 to 30 not shown) Latch Latch HVOUT2 HVOUT31 HVOUT32 Latch Latch

HV5522/HV5530/HV5622/HV5630 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 top view 44-pin J-Lead Package Pin Configurations HV56

44 Pin J-Lead Package

4H V OUT 14 26 Latch Enable 5H V OUT 13 27 Data In 6H V OUT 12 28 Blanking 7H V OUT 11 29 N/C 8H V OUT 10 30 HV OUT 32 9H V OUT 93 1 H V OUT 31

10 HV OUT 83 2 H V OUT 30

11 HV OUT 73 3 H V OUT 29

12 HV OUT 63 4 H V OUT 28

13 HV OUT 53 5 H V OUT 27

14 HV OUT 43 6 H V OUT 26

15 HV OUT 33 7 H V OUT 25

16 HV OUT 23 8 H V OUT 24

17 HV OUT 13 9 H V OUT 23

18 Data Out 40 HV OUT 22

19 N/C 41 HV OUT 21

20 N/C 42 HV OUT 20

21 N/C 43 HV OUT 19

22 Polarity 44 HV OUT 18

4H V OUT 19 26 Latch Enable 5H V OUT 20 27 Data In 6H V OUT 21 28 Blanking 7H V OUT 22 29 N/C 8H V OUT 23 30 HV OUT 1 9H V OUT 24 31 HV OUT 2

10 HV OUT 25 32 HV OUT 3

11 HV OUT 26 33 HV OUT 4

12 HV OUT 27 34 HV OUT 5

13 HV OUT 28 35 HV OUT 6

14 HV OUT 29 36 HV OUT 7

15 HV OUT 30 37 HV OUT 8

16 HV OUT 31 38 HV OUT 9

17 HV OUT 32 39 HV OUT 10

18 Data Out 40 HV OUT 11

19 N/C 41 HV OUT 12

20 N/C 42 HV OUT 13

21 N/C 43 HV OUT 14

22 Polarity 44 HV OUT 15

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 12/13/01 ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. HV5522/HV5530/HV5622/HV5630 4041424344 39 38 37 36 35 34 18 222019 12 13 14 15 16 17 Pin Configurations HV56 44-Pin Quad Plastic Gullwing Package Pin Function 1H V OUT 22 2H V OUT 21 3H V OUT 20 4H V OUT 19 5H V OUT 18 6H V OUT 17 7H V OUT 16 8H V OUT 15 9H V OUT 14

10 HV OUT 13

11 HV OUT 12

12 HV OUT 11

13 HV OUT 10

14 HV OUT 9

15 HV OUT 8

16 HV OUT 7

17 HV OUT 6

18 HV OUT 5

19 HV OUT 4

20 HV OUT 3

21 HV OUT 2

22 HV OUT 1

44-Pin Quad Plastic Gullwing Package Pin Function 1H V OUT 11 2H V OUT 12 3H V OUT 13 4H V OUT 14 5H V OUT 15 6H V OUT 16 7H V OUT 17 8H V OUT 18 9H V OUT 19

10 HV OUT 20

11 HV OUT 21

12 HV OUT 22

13 HV OUT 23

14 HV OUT 24

15 HV OUT 25

16 HV OUT 26

17 HV OUT 27

18 HV OUT 28

19 HV OUT 29

20 HV OUT 30

21 HV OUT 31

22 HV OUT 32

23 Data Out

24 N/C

25 N/C

26 N/C

27 Polarity

28 Clock

30 V DD

31 Latch Enable

32 Data In

33 Blanking

34 N/C

36 HV OUT 2

37 HV OUT 3

38 HV OUT 4

39 HV OUT 5

40 HV OUT 6

41 HV OUT 7

42 HV OUT 8

43 HV OUT 9

44 HV OUT 10

36 HV OUT 31

37 HV OUT 30

38 HV OUT 29

39 HV OUT 28

40 HV OUT 27

41 HV OUT 26

42 HV OUT 25

43 HV OUT 24

44 HV OUT 23

44-pin Quad Plastic Gullwing Package

44-Lead PLCC Package Outline (PJ) Doc. #: DSPD-44PLCCPJ B051607 Symbol A A1 A2 b b1 D D1 E E1 e Dimension (inches) .050 JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. Drawings are not to scale. Note: 1. A Pin 1 identifi er must be located in the index area indicated.The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature. 2. Exact shape of this feature is optional. .150 MAX .048/.042 x 45O .075 MAX 6 40 D E1 E Top View Side View View B A A2 Seating Plane e b Note 1 (Index Area) .056/.042 x 45O 0.20max

3 Places Base

.020 MIN Side View View B Note 2 (3 places)

44-Lead PQFP Package Outline (PG) Doc. #: DSPD-44PQFPPG A031607 Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ θ1 Dimension (mm) 0.80 BSC 0.73 1.95 REF 0.25 BSC 3.5O 5O JEDEC Registration M0-112, Variation AA-2, Issue B, Sep.1995. Note 1: A Pin 1 identifi er must be located in the index area indicated. The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature. Seating Plane Gauge Plane θL View B View B Seating Plane Top View D E b e Side View A2A Note 1 (Index Area D1/4 x E1/4)