HV5523K7-G

HV5523 SUTEX | Alldatasheet

Document overview

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Technical content

Features

► Processed with HVCMOS® technology ► Sink current minimum 100mA ► Shift register speed 16MHz ► Polarity and blanking inputs ► CMOS compatible inputs

Applications

► Inkjet and Electrostatic Print Heads ► AC-Electroluminescent Displays ► MEMS Applications

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com HV5523 Pin Configuration Product Marking L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging HV5523K7 LLLLLLLLL YYWW AAA CCC 44-Lead QFN (K7) (top view)

Ordering Information

(max V) 44-Lead QFN 7.00x7.00mm body, 0.80mm height (max), 0.50mm pitch HV5523 220 HV5523K7-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value Supply voltage, VDD 1 -0.5V to +7.0V Output voltage, HVOUT 1 -0.5V to +230V Logic input levels1 -0.5V to VDD +0.5V Ground current2 1.5A Continuous total power dissipation3 3.4W Operating temperature range -40°C to +85°C Storage temperature range -65°C to +150°C Maximum junction temperature +125°C Thermal resistance (θja)3 29OC/W Notes: 1. Voltages are referenced to VSS. 2. Duty cycle is limited by the total power dissipated in the package. 3. 1.0oz 4-layer 3x4” PCB. Operating Supply Voltages and Conditions Sym Parameter Min Typ Max Units Conditions VDD Logic supply voltage 4.5 - 5.5 V --- HVOUT High voltage output -0.3 - +220 V --- VIH High-level input voltage 0.8VDD - VDD V --- VIL Low-level input voltage 0 - 0.2VDD V --- fCLK Clock frequency - - 16 MHz --- TA Operating free-air temperature -40 - +85 °C --- Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply V DD. 3. Set all inputs to a known state. Power-down sequence should be the reverse of the above. 44-Lead QFN (K7) Package may or may not include the following marks: Si or

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com HV5523 Sym Parameter Min Typ Max Units Conditions IDD VDD supply current - - 25 mA fCLK = 16MHz, fDATA = 8.0MHz IDDQ Quiescent VDD supply current - - 100 µA DIN = 0V, all input logic pins = 0V, all outputs off IO(OFF) Off state output current - - 10 µA All outputs high, all switches parallel IIH High-level logic input current - - 1.0 µA VIH = VDD IIL Low-level logic input current - - -1.0 µA VIL = 0V VOH High level output VDD -1.0V - - V IDOUT = -10mA VOL Low level output HVOUT - - 15 V IHVOUT = +100mA DATA OUT - - 1.0 V IDOUT = +10mA VOC HVOUT clamp voltage - - -1.5 V IOL = -100mA Sym Parameter Min Typ Max Units Conditions fCLK Clock frequency - - 16 MHz --- tW Clock high / low pulse width 31 - - ns --- tSU Data setup time before clock falls 25 - - ns --- tH Data hold time after clock falls 10 - - ns --- tON Turn on time, HVOUT from Enable - - 400 ns RL = 2.0kΩ to VPP max tDHL Delay time clock to data high to low - - 35 ns CL = 15pF tDLH Delay time clock to data low to high - - 35 ns CL = 15pF tDLE Delay time clock to LE low to high 20 - - ns --- tWLE Width of LE pulse 20 - - ns --- tSLE LE set-up time before clock falls 20 - - ns --- CIN Digital logic input capacitance - - 15 pF --- Input and Output Equivalent Circuits VDD DATA INPUT HVOUT Logic Inputs DATA OUTPUT Logic Data Output High Voltage Outputs VDD VSS VSS VSS

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com HV5523 Switching Waveforms LE HVOUT w/ S/R HIGH Data Vali d50%DATA INPUT CLK DATA OUTPUT tSU tH tWH tWL 50% tDLH tDHL 50% tWLEtDLE tSLE 50% 50% 10% tON VIH VIL VIH VIL VOH VOL VOH VOL VIH VIL VOH VOL 50% 50% 50%50%50% Function Table Function Inputs Outputs Data CLK LE BL POL Shift Reg 1 2...32 HV Outputs 1 2...32 Data Out Load latches Transparent latch mode Notes: H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transition * = dependent on previous stage’s state before the last CLK↓ or last LE high.

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com HV5523 Pin # Function Description

1 HVOUT11

High voltage outputs.

2 HVOUT12

3 HVOUT13

4 HVOUT14

5 HVOUT15

6 HVOUT16

7 HVOUT17

8 HVOUT18

9 HVOUT19

10 HVOUT20

11 HVOUT21

12 HVOUT22

13 HVOUT23

14 HVOUT24

15 HVOUT25

16 HVOUT26

17 HVOUT27

18 HVOUT28

19 HVOUT29

20 HVOUT30

21 HVOUT31

22 HVOUT32

23 DATA OUT Data output pin.

24 N/C

No internal connection.25 N/C

26 N/C

27 POL Inverts the polarity of the HVOUT pins

28 CLK Clock pin, shift registers shifts data on falling edge of input clock. 29 VSS Reference voltage, usually ground. 30 VDD Logic supply voltage. 31 LE Latch enable pin, data is shifted from shift register to latches on logic input high. 32 DATA IN Data input pin. 33 BL Blanking pin sets all HVOUT pins ON or OFF depending upon state of polarity. See function table. 34 N/C No internal connection.

35 HVOUT1

High voltage outputs.

36 HVOUT2

37 HVOUT3

38 HVOUT4

39 HVOUT5

40 HVOUT6

41 HVOUT7

42 HVOUT8

43 HVOUT9

44 HVOUT10

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2011 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com HV5523 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV5523 A041511 44-Lead QFN Package Outline (K7) 7.00x7.00mm body, 0.80mm height (max), 0.50mm pitch Symbol A A1 A3 b D D2 E E2 e L L1 θ Dimension (mm) MIN 0.70 0.00 0.20 REF 0.50 BSC 0.45† 0.00 0O JEDEC Registration MO-220, Variation WKKD-3, Issue K, June 2006 * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-44QFNK77X7P050, Version A122309. Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Seating Plane Top View Side View Bottom View A D E L Note 3 Note 2 Note 1 (Index Area D/2 x E/2) View B Note 1 (Index Area D/2 x E/2) b e θx4 View B