HV518 SUTEX | Alldatasheet
Document overview
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Technical content
Features
❏ 32 output lines ❏ 90V output swing ❏ Active pull-down ❏ Latches on all outputs ❏ Up to 6MHz @ VDD = 5V ❏ -40°C to +85°C operation Absolute Maximum Ratings Supply voltage, VDD 1 -0.5V to +6.0V Supply voltage, VPP 1 -0.5V to +90V Logic input levels1 -0.5V to VDD +0.5V Continuous total power dissipation 2,3 1200mW Operating temperature range -40 °C to +85°C Storage temperature range -65 °C to +150°C Lead temperature 1.6mm(1/16 inch) 260 °C from case for 10 seconds Notes: 1. All voltages referenced to GND. 2. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25 °C ambient, derate linearly to 85°C at 20mW/°C. HV518
Ordering Information
The HV518 is designed for vacuum fluorescent or DC plasma applications, where it can serve as a segment, digit or matrix display driver. Each device has 32 outputs, 32 latches and a 32 bit cascadable shift register. Serial data enters the shift register on the LOW-to-HIGH transition of the clock input. With latch enable (LE) HIGH, parallel data is transferred to the output buffers through a 32-bit latch. When LE is low the data is stored in the latch. When STROBE is LOW, all outputs are enabled; if STROBE is HIGH, all outputs are LOW. 12/13/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liabi lity to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to c hange without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most curre nt databook or to the Legal/Disclaimer page on the Supertex website.
Symbol Parameter Min Typ Max Units Conditions IDD Supply current 10 mA V DD = 5V, fCH = 6.0 MHz IDDQ Quiescent supply current 0.5 mA V DD = 5.5V, VIN = 0V IPP Supply current 12 mA Output high, T A = -40°C 71 0m A Output high, TA = 0 to +85°C 500 µA Outputs low VOH High-level output voltage HVoutput 70.0 V I OH= -25mA Serial output 4.5 4.9 5 V V DD = 5V, IOH = -20µA VOL Low-level output HVoutput 5 V I OL= 1mA Serial output 0.06 0.8 V I OL =20µA IIH High-level logic input current 0.1 1 µAV IH = VDD IIL Low-level logic input current -0.1 -1 µAV IL = 0V Note: The total number of ON outputs times the duty cycle must not exceed the allowable package power disspation.
Electrical Characteristics
(over recommended ranges of operating free-air temperature and VDD. Unless otherwise noted, VPP = 80V) Symbol Parameter Min Max Unit Conditions td Delay time, Clock to data output V DD = 4.5V 600 ns C L =15 pF See Figure 4 tDHL Delay time, high-to-low-level, from latch enable V DD = 4.5V 1.5 µs See Figure 5 HVoutput from strobe 1 See Figure 6 tDLH Delay time, low-to-high-level from latch enable V DD = 4.5V 1.5 µs See Figure 5 HVoutput from strobe 1 See Figure 6 tTHL Transition time, high-to-low-level, HVoutput V DD = 4.5V 3 µs See Figure 6 tTLH Transition time, low-to-high-level, HVoutput V DD = 4.5V 2.5 µs See Figure 6 Switching Characteristics (VPP = 80V, CL = 50 pF, TA = 25°C, unless otherwise noted) Symbol Parameter Min Max Units VDD Logic voltage supply 4.5 5.5 V VPP High voltage supply 8 80 V VIH High-level input voltage (See Fig.3.) V DD = 4.5V 3.5 V VIL Low-level input voltage (See Fig. 3.) V DD = 4.5V 1 V IOH High-level output current -25 mA IOL Low-level output current 2 mA fCLK Clock frequency (see Figure 3) V DD = 4.5V 6.0 MHz tw(CKH) Pulse duration , clock high V DD = 4.5V 83 ns tw(CKL) Pulse duration , clock low V DD = 4.5V 83 ns tsu Setup time, data before clock V DD = 4.5V 75 ns th Hold time, data after clock V DD = 4.5V 75 ns TA Operating free-air temperature -40 85 °C Note: Power-up sequence should be the following: 1. Connect ground. 4. Apply V PP. 2. Apply V DD.5 . The VPP should not drop below VDD or float during operation. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. Power-down sequence should be the reverse of the above. Recommended Operating Conditions (TA = 25°C, unless otherwise noted)
XLL * * Previous state VALID IRRELEVANT INVALID VALID PREVIOUSLY STORED DATA NEW DATA VALID VALID Clock Data In SR Contents Latch Enable Latch
Contents
- • • LE Latches HV 1 STB V PP D IN DOUT CLK 32-Bit Shift Register OUT HV 32OUT Input Data In CLK Data Out HH LL X No Change * * Previous state Block Diagram Truth Tables Typical Operating Sequence
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 12/13/010 ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. HV518 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 top view 20 21 top view 40-pin DIP Pin Configurations HV518