HV513WG-G

HV513_13 SUTEX | Alldatasheet

Document overview

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Technical content

Features

► HVCMOS® technology ► Operating output voltage of 250V ► Low power level shifting from 5.0 to 250V ► Shift register speed 8.0MHz @ VDD = 5.0V ► 8 latch data outputs ► Output polarity and blanking ► Output short circuit detect ► Output high-Z control ► CMOS compatible inputs

Applications

► Piezoelectric transducer driver ► Braille driver ► Weaving applications ► Printer drivers ► MEMs ► Displays Typical Application Circuit 8-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs, POL, Hi-Z, and Short Circuit Detect General Description The HV513 is a low voltage serial to high voltage parallel converter with 8 high voltage push-pull outputs. This device has been designed to drive small capacitve loads such as piezoelectric transducers. It can also be used in any application requiring multiple high voltage outputs, with medium current source and sink capabilities. The device consists of an 8-bit shift register, 8 latches, and control logic to perform the polarity select and blanking of the outputs. Data is shifted through the shift register on the low to high transition of the clock. A data output buffer is provided for cascading devices. Operation of the shift register is not affected by the LE, BL, POL, or the HI-Z control inputs. Transfer of data from the shift register to the latch occurs when the LE is high. The data in the latch is stored when LE is low. A high-Z (HI-Z) pin is provided to set all the outputs in a high-Z state. All outputs have short circuit protection that detects if the outputs have reached the required output state. If output does not track the required state, then the SHORT pin will be low. This output will pulse low during the output transistion period under normal operation; see SC Timing Diagram for details. All outputs will have a break-before-make circuitry to reduce cross-over current during output state changes. The POL, BL, LE, and HI-Z inputs have an internal pull up resistor. DIN CLK DOUT LE HiZ POL HVOUT1 HVOUT8 High Voltage Power Supply Supertex HV513 DIN to the next HV513 for cascading Piezo Element BL SHORT FPGA Low Voltage Power Supply Low Voltage Shift Register Latches Output Controller High Voltage Level Translators Push-Pull Output Buffers

Supertex inc. www.supertex.com Doc.# DSFP-HV513 C072413 HV513 Absolute Maximum Ratings Parameter Value Logic supply, VDD -0.5V to 6.0V High voltage supply, VPP VDD to 275V Logic input levels -0.5V to VDD +0.5V Ground current1 0.3A High voltage supply current1 0.25A Continuous total power dissipation2 750mW Operating junction temperature -40°C to +85°C Storage temperature range -65°C to +150°C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: 1. Connection to all power and ground pads is required. Duty cycle is limited by the total power dissipated in the package. 2. For operation above 25°C ambient derate linearly to 85°C at 12mW/°C. Pin Configuration Typical Operating Conditions Sym Parameter Min Typ Max Units Conditions VDD Logic supply voltage 4.5 5.0 5.5 V --- VPP High voltage supply 50 - 250 V Note 1 VIH High-level input voltage VDD -0.9 - VDD V --- VIL Low-level input voltage 0 - 0.9 V --- TJ Operating junction temperature -40 - +85 °C --- Notes: 1. Below minimum VPP the output may not switch. 2. Power-up sequence should be the following: 1. Connect ground 2. Apply V DD 3. Set all inputs (Data, CLK, Enable, etc.) to a known state 4. Apply V PP Power-down sequence should be the reverse of the above Product Marking 32-Lead QFN 1 24 32-Lead QFN (top view) 24-Lead SOW (top view) 24-Lead SOW YY = Year Sealed WW = Week Sealed A = Assembler ID L = Lot Number C = Country of Origin* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW AAA HV513WG LLLLLLLLLL CCCCCCCCCCC HV513 LLLLLL YYWW AAACCC L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging Package may or may not include the following marks: Si or Package may or may not include the following marks: Si or Typical Thermal Resistance Package θja 32-Lead QFN 22OC/W 24-Lead SOW 44OC/W

Ordering Information

Part Number Package Packing HV513K7-G 32-Lead QFN 400/Tray HV513K7-G M935 32-Lead QFN 2000/Reel HV513WG-G 24-Lead SOW 1000/Reel -G denotes a lead (Pb)-free / RoHS compliant package

Supertex inc. www.supertex.com Doc.# DSFP-HV513 C072413 HV513 Sym Parameter Min Typ Max Units Conditions IDD VDD supply current - - 4.0 mA fCLK = 8.0Hz, LE = Low IDDQ Quiescent VDD supply current - - 0.1 mA All VIN = VDD - - 2.0 All VIN = 0V IPP VPP supply current - - 100 µA VPP = 250V, fOUT = 300Hz, no load IPPQ Quiescent VPP supply current - - 100 µA VPP = 240V, outputs are static IIH High-level logic input current - - 10 µA VIH = VDD IIL Low-level logic input current - -10 µA VIL = 0V - - -350 VIL = 0V, for inputs w/pull-up resistors VOH High level output HVOUT 140 - - V VPP = 200V, IHVOUT = -20mA Data out VDD -1.0V - - IDOUT = -0.1mA VOL Low level output HVOUT - - 60 V VDD = 4.5V, IHVOUT = 20mA Data out - - 1.0 IDOUT = 0.1mA Sym Parameter Min Typ Max Units Conditions fCLK Clock frequency 0 - 8.0 MHz --- fOUT Output switching frequency (SOA limited) - 300 - Hz C L = 50nF, VPP = 200V tW Clock width high and low 62 - - ns --- tSU Data setup time before clock rises 15 - - ns --- tH Data hold time after clock rises 30 - - ns --- tWLE Width of latch enable pulse 80 - - ns --- tDLE LE delay time after rising edge of clock 35 - - ns --- tSLE LE setup time before rising edge of clock 40 - - ns --- tOR, tOF HVOUT rise/fall time - - 1000 µs CL = 100nF, VPP = 200V td ON/OFF Delay time for output to start rise/fall - - 500 ns --- tDHL Delay time clock to DOUT high to low - - 110 ns CL = 15pF tDLH Delay time clock to DOUT low to high - - 110 ns CL = 15pF tR, tF All logic inputs - - 5.0 ns --- tSD Output short circuit detection - - 500 ns CL = 15pF, Short to output fall of SHORT tSC Output short circuit clear - - 3000 ns Short clear to output rise of SHORT t HI-Z Output HI-Z state - - 500 ns ---

Supertex inc. www.supertex.com Doc.# DSFP-HV513 C072413 HV513 Input and Output Equivalent Circuits VDD INPUT GND VDD DATA OUT VPP HVOUT HVGNDGND Logic Inputs High Voltage Outputs Logic Data Output 20kΩ* LE POL BL HI-Z HVOUT Within xV of rail Short Detect VH VH VL VL VIL VIH VOH VOL tHi-Z tSD tSC Short Circuit Detect Detail Timing Note: For VPP greater than 150V: Short detect output will flag short conditions - HVOUT is higher than 10V when expected low - HVOUT is lower than VPP - 100V when expected high Short detect output will stay clear - HVOUT is lower than 2.0V when expected low - HVOUT is higher than VPP - 60V when expected high

Supertex inc. www.supertex.com Doc.# DSFP-HV513 C072413 HV513 Switching Waveforms DATA INPUT CLK DATA OUT LE HVOUT w/S/R Low HVOUT w/S/R High VIH VIH VIH VIL VIL VIL VOL VOL VOL VOL VOH VOH VOH VOH 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 90% 10% 10% 90% Data Valid tSU tH tWH tWL tDLH tDHL tSLE tWLE tDLE tOR td(OFF) td(ON) tOR

Supertex inc. www.supertex.com Doc.# DSFP-HV513 C072413 HV513 Function Table Function Inputs Outputs Data CLK LE BL POL HI-Z Shift Reg 1 2...8 HV Outputs 1 2...8 Data Out Store data in latches Transparent mode Outputs High-Z X X X X X L ● ●...● High impedence outputs ● Note: POL, BL, LE, and Hi-Z have internal 20kΩ pull-up resistors. Notes: H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition

• = dependent on previous stage’s state before the last CLK or last LE high. Functional Block Diagram POL BL CLK 8-Bit Static Shift Register

8 Latches

6 Additional

Supertex inc. www.supertex.com Doc.# DSFP-HV513 C072413 HV513 Pin Description - 32-Lead QFN Pin # Function Description NC No internal connection2

4 LGND Low voltage ground

OUT1 High voltage push-pull output

10 HVOUT2 High voltage push-pull output

11 HVOUT3 High voltage push-pull output

12 HVOUT4 High voltage push-pull output

13 HVOUT5 High voltage push-pull output

14 HVOUT6 High voltage push-pull output

15 HVOUT7 High voltage push-pull output

16 HVOUT8 High voltage push-pull output

21 VDD Logic supply voltage

22 DOUT Data output

25 BL Blanking pin, logic input low sets all HV

26 NC No internal connection

27 POL Polarity bar input logic

28 CLK Clock pin, shift registers shifts data on rising edge of input clock

29 LE Latch enable bar input logic

30 SHORT If output does not reach its required state, SHORT pin will output logic low

31 HI-Z High impedance pin, logic input low sets all outputs in a high impedance state

32 DIN Data input

Pad VPP Center pad is at VPP potential. Connect to VPP or leave floating.

Supertex inc. www.supertex.com Doc.# DSFP-HV513 C072413 HV513 Pin # Function Description

1 NC No internal connection

2 VDD Logic supply voltage

3 DOUT Data output

4 BL Blanking pin, logic input LOW sets all HVOUTS low

5 POL Polarity bar input logic

6 CLK Clock pin, shift registers shifts data on rising edge of input clock

7 LE Latch enable bar input logic

8 SHORT If output does not reach its required state, SHORT pin will output logic LOW

9 HI-Z High impedance pin, logic input LOW sets all outputs in a high impedance state

10 DIN Data input

11 LGND Low voltage ground

12 NC No internal connection

15 HVOUT1 High voltage push-pull output

16 HVOUT2 High voltage push-pull output

17 HVOUT3 High voltage push-pull output

18 HVOUT4 High voltage push-pull output

19 HVOUT5 High voltage push-pull output

20 HVOUT6 High voltage push-pull output

21 HVOUT7 High voltage push-pull output

22 HVOUT8 High voltage push-pull output

Pin Description - 24-Lead SOW

Supertex inc. www.supertex.com Doc.# DSFP-HV513 C072413 HV513 32-Lead QFN Package Outline (K7) 6.00x6.00mm body, 0.80mm height (max), 0.50mm pitch Bottom View Seating Plane Top View Side View LC LC LC1 LC Detail C (note 2) Detail A Detail B Detail C 0.30x45 O Detail Bx32 Detail Ax3 (note 2) e e2 e27 x e 7 x e L b 916 32 D E A Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) Symbol A A1 b D D1 E E1 e e1 e2 L L1 LC LC1 Dimension (mm) 0.50 BSC 1.00 REF 0.975 REF 0.20 0.10 REF 0.20 0.25 Drawings not to scale. Supertex Doc. #: DSPD-32QFNK76X6P050, Version B092309. Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. The 4 corner pads are for mechanical placement only, they are not internally connected.

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com HV513 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV513 C072413 24-Lead SOW (Wide Body) Package Outline (WG) 15.40x7.50 body, 2.65mm height (max), 1.27mm pitch Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1 Dimension (mm) 1.27 BSC 0.25 0.40 1.40 REF 0.25 BSC 0O 5O JEDEC Registration MS-013, Variation AD, Issue E, Sep. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-24SOWWG, Version E041309. EE1 D e b A A2 Seating Plane A A Top View Side View Note 1 (Index Area 0.25D x 0.75E1) View B View A-A Seating Plane Gauge Plane L View B θ h h Note 1 Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.