HV508LG-G SUTEX | Alldatasheet
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Features
HVCMOS® technology for high performance Logic-selectable output voltage 100nF drive capability Up to 90VP-P 25µs response time Block Diagram High Voltage Liquid Crystal Shutter Driver General Description The Supertex HV508 is a 45V liquid crystal shutter driver in an 8-Lead SOIC surface mount package. It consists of two outputs that provide square waves of opposite phase. The liquid crystal shutter is connected between the two outputs. Its equivalent load can be approximated as a resistor in parallel with a capacitor. Minimum resistance is 1.0MΩ and maximum capacitance is 0.1µF. The HV508 has three input supply voltages, HV IN, LVIN, and VDD. The output’s amplitude will be either LVIN or HVIN. A logic high on the HVEN input will set the output to operate from the HVIN supply. A logic low on the HV EN input will set the output to operate from the LV IN supply. The output frequency is set by the logic input frequency applied on the POL input. LVIN HVIN VDD HVEN POL GND HVOUT1 HVOUT2 Level Translator Level Translator Level Translator Level Translator CMOS Logic
- 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Ordering Information
8-Lead SOIC (Narrow Body) 4.90x3.90mm body, 1.75mm height (max) 1.27mm pitch HV508 HV508LG-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value HVIN, high voltage input +60V LVIN, low voltage input +7.5V VDD, logic supply voltage +12V Operating temperature -5.0°C to +60°C Storage temperature -65°C to +150°C Soldering temperature1 +300°C Power dissipation2 700mW Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes: Distance of 1.6mm from case for 10 seconds. For operation above 25OC ambient, derate linearly at 6.0mW/OC. Pin Configuration LVIN POL HVEN GND HVOUT1 HVIN VDD HVOUT2 Recommended Operating Conditions Sym Parameter Min Typ Max Units Conditions VDD Logic supply voltage 5.0 - 10.0 V --- LVIN Low output supply voltage 3.0 - 6.0 V --- HVIN High output supply voltage 5.0 - 45 V --- VIL Logic input voltage low 0 - 0.3VDD V --- VIH Logic input voltage high 0.7VDD - VDD V --- TA Ambient temperature -5.0 - +60 °C --- 8-Lead SOIC (LG) (top view) Product Marking 8-Lead SOIC (LG) Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number = “Green” Packaging YWW HV508 LLLL Sym Parameter Min Typ Max Units Conditions IHVQ HVIN quiescent current - - 10 µA --- ILVQ LVIN quiescent current - - 10 µA --- IDDQ VDD quiescent current - - 10 µA --- IHV HVIN operating current - - 2.8 mA POL = 100Hz, HVEN = high, TA = 25OC, Load = 1MΩ in parallel with 0.1µF between HVOUT1 and HVOUT2 ILV LVIN operating current - - 380 µA POL = 100Hz, HVEN = low, TA = 25OC, Load = 1MΩ in parallel with 0.1µF between HVOUT1 and HVOUT2 IIL Logic input current low -5.0 - - µA --- IIH Logic input current high - - 5.0 µA --- CLOAD Output capacitive load* 0 - 0.25 µF CLOAD in parallel with a 1.0MΩ resistor * The device can operate continuously in this range without damage. AC limits are not implemented. Package may or may not include the following marks: Si or
- 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com Power-Up/ Power-Down Sequences Power-up sequence should be the following: Connect GND Connect VDD Connect logic inputs Connect HVIN and connect LVIN Power-down sequence should be the reverse. Logic Truth Table HVEN POL HVOUT1 HVOUT2 H H HVIN GND H L GND HVIN L H LVIN GND L L GND LVIN GND 50% 80% 50% t(OFF)t(ON) POL HVOUT1 VIL VIH HVIN or LVIN LVIN 50% 80% HVEN HVOUT1 VIL VIH HVIN t(ENON) Fig. 1 Fig. 2 Timing Diagrams Sym Parameter Min Typ Max Units Conditions fPOL POL input frequency 0 - 100 Hz --- tHV(ON) Turn-on time when high voltage is enabled - - 16 µs Load = 1.0MΩ in parallel with 0.1µF between HVOUT1 and HVOUT2, HVEN = high, outputs rise to HVIN. See Fig.1.tHV(OFF) Turn-off time when high voltage is enabled - - 16 µs tLV(ON) Turn-on time when high voltage is disabled - - 40 µs Load = 1.0MΩ in parallel with 0.1µF between HVOUT1 and HVOUT2, HVEN = low, outputs rise to HVIN. See Fig.1.tLV(OFF) Turn-off time when high voltage is disabled - - 6.0 µs tEN(ON) Turn-on time from HVEN to HVOUT - - 25 µs Load = 1.0MΩ in parallel with 0.1µF between HVOUT1 and HVOUT2. See Fig.2.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications ©2009 All rights reserved. Unauthorized use or reproduction is prohibited .
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888 www.supertex.com HV508 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV508 A042709 8-Lead SOIC (Narrow Body) Package Outline (LG) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch Seating Plane Gauge Plane L E D e b A A2 Seating Plane A A Top View Side View View B View B θ Note 1 (Index Area D/2 x E1/2) View A-A h h Note 1 Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1 Dimension (mm) 1.27 BSC 0.25 0.40 1.04 REF 0.25 BSC 0O 5O JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-8SOLGTG, Version I041309. Note: This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.