HV506

HV506 SUTEX | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 9

Technical content

Features

❏ Processed with HVDI  technology ❏ Symmetric row drive ❏ Output voltage up to 275V ❏ Source/Sink current 300mA (min.) ❏ Shift Register Speed 3MHz ❏ Pin-programmable shift direction (DIR) ❏ Hi-Rel processing available Absolute Maximum Ratings Logic supply voltage, LVDD 1 -0.5V to +15V Output supply voltage, VDD 1 -0.5V to +15V Substrate bias voltage, Vsub See Note 3 Output voltage, HVOUT ±300V Logic input levels -0.5V to V DD +0.5V Continuous total power dissipation2 Ceramic 1900mW Plastic 1200mW Operating temperature range Plastic -40 °C to +85°C Ceramic -55°C to +125°C Storage temperature range -65 °C to +150°C Lead temperature 1.6mm (1/16 inch) 260 °C from case for 10 seconds Notes: 1. All voltages are referenced to V SS. 2. For operation above 25 °C ambient derate linearly to maximum operating temperture at 20mW/°C for plasitc and at 19mW/°C for ceramic. 3. V sub must be the most positive with respect to VSS.

Ordering Information

HV506 HV506DG HV506PG HV506X 275V 40-Channel Row Driver with SCR Outputs

Electrical Characteristics

(over recommended operating conditions of VDD = 12V, LVDD = 12V, and TA = 25°C unless noted) Symbol Parameter Min Max Units Conditions IDD VDD supply current 10 mA f CLK = 3MHz IDDQ Quiescent VDD supply current 100 µA All VIN = VSS or VDD VOH High-level output HV OUT VDD-10 V I O= -300mA Data out 10.8 V I O= -100µA VOL Low-level output HV OUT VSS+10 V I O= 300mA Data out 1.2 V I O= 100µA IIH High-level logic input current 1 µAV IH = VDD IIL Low-level logic input current -1 µAV IL = VSS IOFF Output OFF leakage current (High-Z) 10 µAH V OUT - VSS = 275V, Vsub = HVOUT 10 µAV DD - HVOUT = 275V, Vsub = VDD Notes: 1. Only one output can be turned on at a time. DC Characteristics Symbol Parameter Min Max Units Conditions VOH High-level output V DD-10 V I O= -300mA VOL Low-level output V SS+10 V I O= 300mA IL Latching Current 15 mA VL Latching Voltage 100 V IH Holding Current 10 mA VH Holding Voltage 10 V IOFF Output OFF leakage current (High-Z) 10 µAH V OUT - VSS = 275V, Vsub = HVOUT 10 µAV DD - HVOUT = 275V, Vsub = VDD SCR Characteristics

Symbol Parameter Min Max Units Conditions fCLK Clock frequency 3 MHz tW (H/L) Pulse width - clock high or low 150 ns tSUD Data set-up time before clock rises 50 ns tHD Data hold time after clock rises 50 ns tSUC HVOUT delay from clock rises (Hi-Z to H or L) 1 µsC L = 10nF tSUE HVOUT delay from Output Enable rises 600 ns C L = 10nF tHC HVOUT delay from clock rises (H or L to Hi-Z) 2 µsC L = 10nF tHE HVOUT delay from Output Enable rises 600 ns C L = 10nF tDHL * Delay time clock to data output falls 250 ns C L = 15pF tDLH * Delay time clock to data output rises 250 ns C L = 15pF tOFF(SCR) Turn off time of output SCR 4 µs Time after IOUT ≤ 2mA, CL = 10nF tOFF(D) Turn off time of output diode 2 µs Time after IOUT ≤ 2mA, CL = 10nF tPOW POL pulse width 3 µs tOEW Output Enable pulse width 3 µs SR Slew rate of HV OUT 200 V/ µs AC Characteristics * The delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. There is an internal delay for the data output which is equal to tWH. Therefore the delay is measured from the trailing edge of the clock. HV506

Symbol Parameter Min Max Units LVDD Logic supply voltage 10.8 13.2 V VDD Output supply voltage 10.8 13.2 V VIH High-level input voltage 0.8LV DD LVDD V VIL Low-level input voltage 0 0.2LV DD V fCLK Clock frequency 3 MHz IO High voltage output current ±300 mA TA Operating free-air temperature Plastic -40 +85 °C Ceramic -55 +125 °C IOD Allowable pulse current through diodes ±500 mA Notes: The substrate pin Vsub (pin 39) must be biased for proper output breakdown voltage. Vsub ≥ VDD or HVOUT whichever is higher. LVDD/VDD are measured with respect to LVSS/VSS. Recommended Operating Conditions LVDD LVSS Input VDD HVOUT DN DP VSS Logic Inputs Data Out Logic Data Output High Voltage Outputs LVDD LVSS Input and Output Equivalent Circuits SCR Characteristics VLVH IL IH I V HV506

(DRIOA/DRIOB) 50% 50% tPOW Data Reset Output (DRIOA/DRIOB) tHD 50% 50% VIH VIL 90% 10% HVOUT HVOUT tSUE 90% tHE 10% 50% tDLH 50% tDHL 50% tOEW 50% High ImpedanceHigh Impedance High ImpedanceHigh Impedance 90% 10% tSUC 90% tHC 10% HVOUT (POL = H) HVOUT (POL = L) POL OE Data Valid tSUD CLK tWL 1/fCLK 50% 50% 50%50% tWH tSUC tHC tSUE tHE VIH VIL VOH VOH VOL VIH VIL VOL VIH VIL VOH VOL

DIR Data Reset In Data Reset Out HV OUT # Sequence Direction 3 LD R IOB DRIOA 1 40 → 1 HD R IOA DRIOB 2 1 → 40 CLK S/R DIR DRIOB Output Output Output VDD LVSS VSS DP HVOUT1 HVOUT2 HVOUT40 DN LVDD DRIOA OE POL Functional Block Diagram Function Table I/O Relations Inputs CLK DIR S/R Data POL OE HV Outputs O/P HIGH X X H H L H O/P OFF X X L X L HIGH-Z O/P LOW X X H L L L O/P OFF X X X X H All O/P HIGH-Z Note: H = logic high level, L = logic low level, X = irrelevant Output Sequence Operation Table Notes: 1. DR IOA is DRIOBdelayed by 40 clock pulses. 2. DRIOB is DRIOA delayed by 40 clock pulses. 3. Reference to chip layout drawing.

Typical Output Circuit Connections Substrate Bias Operation In order to achieve the desired output breakdown voltage, the substrate must be biased to the most positive potential of any circuit node. For this condition, V sub ≥ VDD or HVOUT whichever is higher. Refer to Typical Output Circuit Connections for wiring. A typical Vsub signal is shown below. + HV Vsub Vcolumns -HV 0VVSS HVOUT VDD VSS D2D1D4 Sink SCR Source SCR HV506 -HV +HV 12V GND DN DP LVDD LVSS Note: The voltage potential between LV DD/VDD and LVSS/VSS must not exceed recommended operating conditions of 10.8V - 13.2V (12V typical) Note: In general, when driving the outputs positive, V SUB = +HV. And when driving outputs negative, V SUB equals most positive voltage; e.g. GND or >0V.

+ HV - (VDD - VSS) VSS - HV High Impedance High Impedance High Impedance Output n Output n+1 Sink* SCR Source* SCR D2* tOFF (D2) D1* Drive Current Disabled Drive Current Disabled tOFF (D1) tOFF (Sink SCR) tOFF (Source SCR) HV Switching Waveforms and Operation To drive a TFEL row with a negative pulse: The desired sink SCR is enabled and V SS is connected to -HV via a current limited switch. After holding the output at the -HV level, the switch is opened in order to set the sink SCR current to zero. The row is then discharged through a discharge diode when D2 is switched to GND. The application of a positive pulse to a row operates in a similar manner using the selected source SCR and D 1. * Notes internal device handling current flow. Refer to Typical Output Circuit Connections for schematic.

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 12/13/010 ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. HV506 Option A: Pin Function Pin Function 1H V OUT13 3 O E 2H V OUT 23 4 POL 3H V OUT 33 5 L V DD 4H V OUT 43 6 V SS 5H V OUT 53 7 V DD 6H V OUT 63 8 L V SS 7H V OUT 73 9 V sub 8H V OUT 84 0 N/C 9H V OUT 94 1 N/C

10 HV OUT 10 42 D N

11 HV OUT 11 43 D P

12 HV OUT 12 44 N/C

13 HV OUT 13 45 HV OUT 21

14 HV OUT 14 46 HV OUT 22

15 HV OUT 15 47 HV OUT 23

16 HV OUT 16 48 HV OUT 24

17 HV OUT 17 49 HV OUT 25

18 HV OUT 18 50 HV OUT 26

19 HV OUT 19 51 HV OUT 27

20 HV OUT 20 52 HV OUT 28

21 N/C 53 HV OUT 29

22 D P 54 HV OUT 30

23 D N 55 HV OUT 31

24 N/C 56 HV OUT 32

25 N/C 57 HV OUT 33

26 LV SS 58 HV OUT 34

27 V DD 59 HV OUT 35

28 DIR 60 HV OUT 36

29 V SS 61 HV OUT 37

30 CLOCK 62 HV OUT 38

31 DR IOA 63 HV OUT 39

32 DR IOB 64 HV OUT 40

Note: Pins 65–80 are NC. Pin Configurations Package Outline Index 25 40 top view 3-sided Plastic 64-pin Gullwing Package HV506