HV4522PJ

HV4522 SUTEX | Alldatasheet

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Technical content

Features

Processed with HVCMOS Technology Output voltages to -220V Source current minimum 60 mA Shift register speed 8 MHz Polarity and blanking inputs CMOS compatible inputs Forward and reverse shifting options 44-lead plastic and ceramic surface mount packages Hi-Rel processing available Can be used with the HV55 and HV56 to provide 220V push pull operation General Description The HV4522 and HV4622 are low-voltage serial to high-voltage parallel converters with P-Channel open drain outputs. These devices have been designed for use as drivers for AC-electrolu- minescent displays. They can also be used in any application requiring multiple output high-voltage current source capabilities such as driving inkjet and electrostatic print heads, plasma panels, or vacuum fluorescent displays. These devices consist of a 32-bit shift register, 32 data latches, and control logic to perform polarity and blanking functions. Data is shifted through the shift register on the logic high-to-low transition of the clock. The HV4522 shifts in the counterclockwise direction when viewed from the top of the package and the HV4622 shifts in the clockwise direction. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. The data in the shift register is latched when the latch enable pin is brought to logic high and then returned to ground. If the latch enable pin is held high, the latch becomes transparent and the shift register data is directly reflected in the outputs. For applications requiring active pull down as well as pull up, the HV4522 and HV4622 can be paired with the HV55 and HV56 devices, respectively. Absolute Maximum Ratings1 Supply voltage, VDD +0.5V to -16V Off state output voltage HV4522/ HV4622 +0.5V to -240V Logic input levels +0.5V to VDD - 0.3V Ground current2 1.5A Continuous total power dissipation 3 Plastic 1200mW Ceramic 1500mW Operating temperature range Ceramic -55°C to +125°C Plastic -40°C to +85°C Storage temperature range -65°C to +150°C Lead temperature 1.6mm (1/16 inch) 260°C from case for 10 seconds Notes: All voltages are referenced to VSS. Duty cycle is limited by the total power dissipated in the package. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C for plastic and at 15mW/°C for ceramic. HV4522 HV4622 32-Channel Serial To Parallel Converter with P-Channel Open Drain Outputs Package Options

44 J-Lead Quad

44 Quad Plastic

-220 HV4522DJ HV4522PJ HV4522PG HV4522X HV4622 -220 HV4622DJ HV4622PJ HV4622PG HV4622X

Ordering Information

Data set-up time before clock rises ns tH Data hold time after clock rises ns tON Turn ON time, HVOUT from enable 400 ns RL = 10K to VOO MAX tDHL Delay time clock to data high to low 100 ns CL = 15pF tDLH Delay time clock to data low to high 100 ns CL = 15pF tDLE Delay time clock to LE low to high ns tWLE Width of LE pulse ns tSLE LE set-up time before clock falls ns Symbol Parameter Min Max Units Conditions IDD VDD supply current -15 mA fCLK = 8 MHz FDATA = 4 MHz IDDQ Quiescent VDD supply current -100 µA VIN = VSS or VDD IO(OFF) Off state output current -100 µA All SWS parallel IIH High-level logic input current µA VIH = VDD IIL Low-level logic input current µA VIL = VSS VOH High-level output data out VDD + 1.0V V IDout = -100µA VOL Low-level output voltage HVOUT -30.0 V IHVout = -60mA Data out -1.0 V IDout = -100µA VOC HVOUT clamp voltage +1.5 V IOL = +60mA Electrical Characteristics1 (over recommended operating conditions unless noted) HV4522/HV4622 DC Characteristics AC Characteristics (VDD = -12V, TC = 25°C) Recommended Operating Conditions Symbol Parameter Min Max Units VDD Logic supply voltage -10.8 -13.2 V HVOUT Output off voltage HV4522 and HV4622 +0.3 -220 V VIH High-level input voltage (LOGIC “1”) VDD + 2V VDD V VIL Low-level input voltage (LOGIC “0”) -2.0 V fCLK Clock frequency MHz TA Operating free-air temperature Plastic -40 +85 Ceramic -55 +125 Note: All voltages are referenced to VSS.

50% 50% Data Input Clock 50% 50% 50% tSU tH tWH tWL 50% 50% tDHL tDLH 50% tWLE tDLE tSLE 50% 50% tON HVOUT w/ S/R HIGH 10% VSS VSS-12 VSS VSS-12 VSS VSS-12 VSS VSS-12 VSS VSS-12 VSS VOO Data Out VSS Input VSS HVOUT Logic Inputs Data Out Logic Data Output High Voltage Output VSS VDD VDD HV4522/HV4622 Input and Output Equivalent Circuits Switching Waveforms

(Outputs 3 to 30 not shown) Latch Latch HVOUT2 HVOUT31 HVOUT32 Latch Latch VSS Functional Block Diagram HV4522/HV4622 Function Table Inputs Outputs Function Shift Reg HV Outputs Data Out 2…32 2…32 All on X X X L L *…* H H…H All off X X X L H *…* L L…L Invert mode X X L H L *…* *…* Load S/R H or L L H H H or L *…* *…* X H or L H H *…* *…* X H or L H L *…* *…* L H H H L *…* L *…* H H H H H *…* H *…* Notes: H = high level = -12V, L = low level = 0V, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transition. * = dependent on previous stage’s state before the last CLK high-to-low transition or last LE high. Data CLK LE BL POL Load latches Transparent latch mode

39 38 37 36 35 34 33 32 31 30 29 10 11 12 13 14 15 16 17 top view 44-pin J-Lead Package Pin Configurations HV4522/HV4622 HV4522

44 Pin J-Lead Package

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 222-8888 • FAX: (408) 222-4895 www.supertex.com 05/01/03rev.2 ©2003 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 39 38 37 36 35 34 12 13 14 15 16 17 top view 44-pin PQFP Package HV4522 44-Pin Plastic Gullwing (QFP) Package Pin Function HVOUT 12 HVOUT 13 HVOUT 14 HVOUT 15 HVOUT 16 HVOUT 17 HVOUT 18 HVOUT 19 HVOUT 20 HVOUT 21 HVOUT 22 HVOUT 23 HVOUT 24 HVOUT 25 HVOUT 26 HVOUT 27 HVOUT 28 HVOUT 29 HVOUT 30 HVOUT 31 HVOUT 32 N/C Package Outline Pin Configurations HV4522/HV4530/HV4622/HV4630 Pin Function Data Out N/C N/C N/C Polarity Clock VSS VDD Latch Enable Data In Blanking HVOUT 1 HVOUT 2 HVOUT 3 HVOUT 4 HVOUT 5 HVOUT 6 HVOUT 7 HVOUT 8 HVOUT 9 HVOUT 10 HVOUT 11 HV4622 44-Pin Plastic Gullwing (QFP) Package Pin Function HVOUT 21 HVOUT 20 HVOUT 19 HVOUT 18 HVOUT 17 HVOUT 16 HVOUT 15 HVOUT 14 HVOUT 13 HVOUT 12 HVOUT 11 HVOUT 10 HVOUT 9 HVOUT 8 HVOUT 7 HVOUT 6 HVOUT 5 HVOUT 4 HVOUT 3 HVOUT 2 HVOUT 1 N/C Pin Function Data Out N/C N/C N/C Polarity Clock VSS VDD Latch Enable Data In Blanking HVOUT 32 HVOUT 31 HVOUT 30 HVOUT 29 HVOUT 28 HVOUT 27 HVOUT 26 HVOUT 25 HVOUT 24 HVOUT 23 HVOUT 22