HV430WG-G

HV430_14 SUTEX | Alldatasheet

Document overview

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Technical content

Features

► 105Vrms ring signal ► Output overcurrent protection ► 5.0V CMOS logic control ► Logic enable/disable to save power ► Adjustable deadband in single-control mode ► Power-on reset ► Fault output for problem detection

Applications

► Line access cards ► Set-top/Street box General Description The Supertex HV430 is a high voltage PWM ring generator integrated circuit. The high voltage outputs, V PGATE and VNGATE, are used to drive the gates of external high voltage N-channel and P-channel MOSFETs in a push-pull configuration. Overcurrent protection is implemented for both the P-channel and N-channel MOSFETs. External sense resistors set the over-current trip point. High-Voltage Ring Generator The RESET input functions as a power-on reset when connected to an external capacitor. The FAULT output indicates an overcurrent condition and is cleared after 4 consecutive cycles with no overcurrent condition. A logic low on RESET or ENABLE clears the FAULT output. It is active- low and open-drain to allow wire OR’ing of multiple drivers. P GATE and N GATE are controlled independently by logic inputs PIN and NIN when the MODE pin is at logic high. A logic high on PIN will turn on the external P-channel MOSFET. Similarly, a logic high on NIN will turn on the external N-channel MOSFET. Lockout circuitry prevents the N and P switches from turning on simultaneously. A pulse width limiter restricts pulse widths to no less than 100 - 200ns. For applications where a single control input is desired, the MODE pin should be connected to SGND. The PWM control signal is then input to the N IN pin. A user-adjustable deadband in the control logic ensures break-before-make on the outputs, thus avoiding cross conduction on the high voltage output during switching. A logic high on N IN will turn the external P- Channel MOSFET on and the N-Channel off, and vice versa. The IC can be powered down by applying a logic low on the ENABLE pin, placing both external MOSFETs in the off state. Functional Block Diagram Ringer Output RSENSE RSENSE VDD Down Translator N Driver FAULT PIN NIN RESET De-glitcher DEADBAND ENABLE MODE VDD Control Logic VNN1 VPP1 SIG GND VDD Current Trip PWR GND +5.0V VPP1 VPP2 VPSEN VPGATE VNN1 VNN2 VNSEN VNGATE 10µA resetclk VNN2 Regulator Up Translator P Driver Up Translator Down Translator Current Trip VPP2 Regulator

Supertex inc. www.supertex.com Doc.# DSFP-HV430 A031414 Pin Configuration Product Marking 20-Lead SOW (top view) Absolute Maximum Ratings Parameter Value VPP1 - VNN1, power supply voltage +340V VPP1, positive high voltage supply +220V VPP2, positive gate voltage supply +220V VNN1, negative high voltage supply -220V VNN2, negative gate voltage supply -220V VDD, logic supply +7.5V Operating temperature range -40OC to +85OC Storage temperature range -65OC to +150OC Power dissipation 600mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 20 20-Lead SOW YY = Year Sealed WW = Week Sealed A = Assembler ID L = Lot Number C = Country of Origin* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW AAA HV430WG LLLLLLLLLL CCCCCCCCCCC Sym Parameter Min Typ Max Units Conditions External Supplies VPP1 High voltage positive supply 50 - 200 V --- IPP1Q VPP1 quiescent current - 250 500 µA PIN = NIN = 0V IPP1 VPP1 operating current - - 2.0 mA No load, VOUTP and VOUTN switching at 100KHz VNN1 High voltage negative supply VPP1 -325 - -50 V --- INN1Q VNN1 quiescent current - 250 500 µA PIN = NIN = 0V, RDB = 18kΩ INN1 VNN1 operating current - - 1.0 mA No load, VOUTP and VOUTN switching at 100KHz VDD Logic supply voltage 4.50 - 5.50 V --- IDDQ VDD quiescent current - 300 400 µA PIN = NIN = 0V, RDB = 18kΩ IDD VDD operating current - - 1.0 mA PIN = NIN = 100KHz, RDB = 18kΩ Electrical Characteristics (Over operating supply voltage unless otherwise specified. TA = -40°C to +85°C) Package may or may not include the following marks: Si or

Ordering Information

Part Number Package Option Packing HV430WG-G 20-Lead SOW 1000/Reel Typical Thermal Resistance Package θja 20-Lead SOW 66OC/W -G denotes a lead (Pb)-free / RoHS compliant package

Supertex inc. www.supertex.com Doc.# DSFP-HV430 A031414 Sym Parameter Min Typ Max Units Conditions Internal Supplies VPP2 Positive linear regulator output voltage VPP1 -16 - VPP1 -10 V --- VNN2 Negative linear regulator output voltage V PP1 +10 - VPP1 +14 V --- Positive High Voltage Output VPGATE Output voltage swing VPP2 - VPP1 V No load on VPGATE RSOURCEP VPGATE source resistance - - 12.5 Ω IOUT = 80mA RSINKP VPGATE sink resistance - - 12.5 Ω IOUT = -80mA tRISEP VPGATE rise time - - 50 ns CLOAD = 1.4nF tFALLP VPGATE fall time - - 50 ns CLOAD = 1.4nF tPWP(MIN) VPGATE minimum pulse width (internally limited) 100 150 200 ns --- tDELAYP PIN to PGATE delay time - - 300 ns Mode = 1 VPSEN VPGATE current sense voltage VPP1 -0.85 VPP1 -1.0 VPP1 -1.15 V --- tSHORTP VPGATE current sense off time - - 150 ns --- Negative High Voltage Output VNGATE Output voltage swing VNN2 - VNN1 V No load on VNGATE RSOURCEN VNGATE source resistance - - 15.0 Ω IOUT = 80mA RSINKN VNGATE sink resistance - - 15.0 Ω IOUT = 80mA tRISEN VNGATE rise time - - 50 ns CLOAD = 1.4nF tFALLN VNGATE fall time - - 50 ns CLOAD = 1.4nF tPWN(MIN) VNGATE minimum pulse width (internally limited) 100 150 200 ns --- tDELAYN NIN to NGATE delay time - - 300 ns Mode = 1 VNSEN VNGATE current sense voltage VNN1 +0.85 VNN1 +1.0 VNN1 +1.15 V --- tSHORTN VNGATE current sense off time - - 150 ns --- Control Circuitry VIL Logic input low voltage 0 - 0.60 V VDD = 5.0V VIH Logic input high voltage 2.7 - 5.0 V VDD = 5.0V IINDN Input pull-down current 0.5 1.0 5.0 µA PIN, NIN, ENABLE RUP Input pull-up resistance 100 200 300 KΩ MODE VOL Logic output low voltage - - 0.50 V VDD = 5.0V, IOUT = -0.5mA VOH Logic output high voltage 4.50 - - V VDD = 5.0V, IOUT = +0.5mA VRST(OFF) RESET voltage, device off 3.2 - 3.5 V VDD = 5.0V VRST(ON) RESET voltage, device on 3.7 - 4.0 V VDD = 5.0V Electrical Characteristics (cont.)(Over operating supply voltage unless otherwise specified. TA = -40°C to +85°C)

Supertex inc. www.supertex.com Doc.# DSFP-HV430 A031414 Sym Parameter Min Typ Max Units Conditions VRST(HYS) RESET hysteresis voltage 0.3 - - V VDD = 5.0V IRESET RESET pull-up current 7.0 10 13 µA VRESET = 0 - 4.5V tRST(ON) RESET on delay - - 1.0 µs --- tRST(ON) RESET off delay - - 1.0 µs --- tEN(ON) ENABLE on delay 50 100 150 µs --- tEN(OFF) ENABLE off delay - - 1.0 µs --- tFLT(HOLD) FAULT hold time - 4 - NIN/PIN cycles ENABLE = 1 tDB Deadband time 35 50 70 ns Mode = 0, RDB = 5.6kΩ 105 140 175 Mode = 0, RDB = 18kΩ tDELAY(N-P) N-off to P-on transistion delay - - 300 ns Mode = 0, RDB < 27kΩ tDELAY(P-N) P-off to N-on transistion delay - - 300 ns Mode = 0, RDB < 27kΩ ∆tDELAY(N-P) Delay difference: tdelayN(off) - tdelayP(on) -80 0 80 ns Mode = 1 ∆tDELAY(P-N) Delay difference: tdelayP(off) - tdelayN(on) -80 0 80 ns Mode = 1 Electrical Characteristics (cont.)(over operating supply voltage unless otherwise specified. TA = -40°C to +85°C) Truth Table Logic Inputs* RESET Output NIN PIN Mode EN Externel N-Channel MOSFET Externel P-Channel MOSFET L L H H >VRESET(ON) OFF OFF L H H H >VRESET(ON) OFF ON H L H H >VRESET(ON) ON OFF H H H H >VRESET(ON) OFF OFF H X L H >VRESET(ON) OFF ON L X L H >VRESET(ON) ON OFF X X X L X OFF OFF X X X X <VRESET(OFF) OFF OFF Note: * Unused logic inputs should be connected to VDD or GND.

Supertex inc. www.supertex.com Doc.# DSFP-HV430 A031414 Dual-Control Mode Timing Single-Control Mode Timing tP RISE tN-P DELAY tP-N DELAY tN RISE tN-P DEADBAND NIN POUT NOUT tP FALL tN FALL tP-N DEADBAND ON OFF ON OFF VDD GND VPP2 VPP1 VNN2 VNN1 OFF ON OFF ON tP DELAY(OFF) NIN POUT NOUT VNN1 VNN2 VPP1 VDD GND PIN VPP2 VDD GND tP DELAY(ON) tP PULSE(MIN) tP RISE tP FALL tN DELAY(OFF)tN DELAY(ON) tN PULSE(MIN) tN RISE tN FALL

Supertex inc. www.supertex.com Doc.# DSFP-HV430 A031414 ENABLE Timing RESET Timing OFF ON OFF ON Off Switching Off Switching Off Switching Off NIN/PIN POUT NOUT VNN1 VNN2 VPP1 VPP2 GND VDD GND VDD tEN(ON) tEN(OFF) NIN/PIN POUT NOUT OFF ON OFF ON VNN1 VNN2 VPP1 VPP2 GND VDD RESET VRESET(ON) GND tRST(ON) Off Switching Off Switching Off Switching Off tRST(OFF) VRESET(OFF)

Supertex inc. www.supertex.com Doc.# DSFP-HV430 A031414 NIN POUT NOUT OFF ON OFF ON VNN1 VNN2 VPP1 GND VDD NSENSE FAULT w/ext pull-up OK Over Note: NSENSE overcurrent shown. PSENSE operates identically. ENABLE or RESET 0 GND VDD VPP2 tFAULT(HOLD) ENABLE or RESET clears fault immediately. GND VDD FAULT Timing

Supertex inc. www.supertex.com Doc.# DSFP-HV430 A031414 Pin Description Pin # Name Description 1 VDD Logic supply voltage. 2 FAULT Logic output. Fault is at logic low when either current limit sense pin, VPSEN or VNSEN, is acti- vated. Remains active until overcurrent condition clears or ENABLE = 0 or RESET = 0.

3 MODE

Logic mode input. 0 = single-control; 1 = dual-control. When MODE is high, NIN and PIN inde - pendently control NOUT and POUT, respectively. When MODE is low, NIN controls both outputs in a complementary manner. (See Truth Table) 4 PIN Logic control input. When mode is high, logic input high turns on the external high voltage P-chan- nel MOSFET. Internally pulled low. 5 NIN Logic control input. When mode is high, logic input high turns on the external high voltage N-chan- nel MOSFET. Internally pulled low. 6 ENABLE Logic enable input. Logic high enables IC. Internally pulled low.

7 RESET

Power-on reset. A capacitor connected between this pin and ground determines the delay time between application of VDD and when the device outputs are enabled. Low leakage tantalum recommended.

8 DEADBAND

A resistor between this pin and ground sets the ‘break-before-make’ time between output transi- tions. Applicable only in single-control mode. For minimum deadtime, a 5.6kΩ resistor to ground should be used. For dual-input mode, tie to VDD. 9 SGND Low voltage logic ground. 10 PGND High voltage logic ground. 11 VNN2 Negative gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should beconnected between VNN2 and VNN1. 12 VNN1 Negative high voltage supply. 13 VNSEN Pulse by pulse over current sensing for N-Channel MOSFET. 14 VNGATE Gate drive for external N-channel MOSFET. N/C No connect. 17 VPGATE Gate drive for external P-channel MOSFET. 18 VPSEN Pulse by pulse over current sensing for P-Channel MOSFET. 19 VPP1 Positive high voltage supply. 20 VPP2 Positive gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should beconnected between VPP2 and VPP1.

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) HV430 Doc.# DSFP-HV430 A031414 20-Lead SOW (Wide Body) Package Outline (WG) 12.80x7.50mm body, 2.65mm height (max), 1.27mm pitch Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1 Dimension (mm) 1.27 BSC 0.25 0.40 1.40 REF 0.25 BSC 0O 5O JEDEC Registration MS-013, Variation AC, Issue E, Sep. 2005. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-20SOWWG, Version D041309. EE1 D e b A A2 Seating Plane A A Top View Side View Note 1 (Index Area 0.25D x 0.75E1) View B View A-A Seating Plane Gauge Plane L View B θ h h Note 1 Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.