HV430

HV430 SUTEX | Alldatasheet

Document overview

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Technical content

Features

❏ 105Vrms ring signal ❏ Output over current protection ❏ 5.0V CMOS logic control ❏ Logic enable/disable to save power ❏ Adjustable deadband in single-control mode ❏ Power-on reset ❏ Fault output for problem detection

Applications

❏ Line access cards ❏ Set-top/Street box General Description The Supertex HV430 is a high voltage PWM ring generator integrated circuit. The high voltage outputs, V PGATE and VNGATE, are used to drive the gates of external high voltage P-channel and N-channel MOSFETs in a push-pull configuration. Over current protection is implemented for both the P-channel and N- channel MOSFETs. External sense resistors set the over-cur- rent trip point. The RESET input functions as a power-on reset when connected to an external capacitor. The FAULT output indicates an over-current condition and is cleared after 4 consecutive cycles with no overcurrent condition. A logic low on RESET or ENABLE clears the FAULT output. It is active-low and open-drain to allow wire OR’ing of multiple drivers. P gate and Ngate are controlled independently by logic inputs PIN and NIN when the MODE pin is at logic high. A logic high on PIN will turn on the external P-channel MOSFET. Similarly, a logic high on NIN will turn on the external N-channel MOSFET. Lockout circuitry prevents the N and P switches from turning on simultaneously. A pulse width limiter restricts pulse widths to no less than 100- 200ns. For applications where a single control input is desired, the MODE pin should be connected to SGND. The PWM control signal is then input to the N IN pin. A user-adjustable deadband in the control logic ensures break-before-make on the outputs, thus avoiding cross conduction on the high voltage output during switching. A logic high on N IN will turn the external P-Channel MOSFET on and the N-Channel off, and vice versa. The IC can be powered down by applying a logic low on the ENABLE pin, placing both external MOSFETs in the off state. Absolute Maximum Ratings VPP1 – VNN1, power supply voltage +340V VPP1, positive high voltage supply +220V VPP2, positive gate voltage supply +220V VNN1, negative high voltage supply -220V VNN2, negative gate voltage supply -220V VDD, logic supply +7.5V Storage temperature -65 °C to +150°C Power dissipation 600mW

Ordering Information

Operating Voltage Package Options VPP1-VNN1 SOW-20 325V HV430WG 12/13/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liabi lity to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to c hange without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most curre nt databook or to the Legal/Disclaimer page on the Supertex website.

Electrical Characteristics

(Over operating supply voltage unless otherwise specified, T A = -40°C to +85°C.) External Supplies Symbol Parameter Min Typ Max Unit Conditions VPP1 High voltage positive supply 50 200 V IPP1Q VPP quiescent current 250 500 µAP IN=NIN=0V IPP1 VPP operating current 2.0 mA No load VOUTP and VOUTN switching at 100kHz VNN1 High voltage negative supply V PP1-325 -50 V INN1Q VNN1 quiescent current 250 500 µAP IN=NIN=0V, RDB =18kΩ INN1 VNN1 operating current 1.0 mA No load VOUTP and VOUTN switching at 100kHz VDD Logic supply voltage 4.50 5.50 V IDDQ VDD quiescent current 300 400 µAP IN=NIN=0V, RDB =18kΩ IDD VDD operating current 1.0 mA P IN=NIN=100kHz, RDB =18kΩ Internal Supplies Symbol Parameter Min Typ Max Unit Conditions VPP2 Positive linear regulator output voltage V PP1-16 V PP1-10 V VNN2 Negative linear regulator output voltage V NN1+10 V NN1+14 V Positive High Voltage Output Symbol Parameter Min Typ Max Unit Conditions VPgate Output voltage swing V PP2 VPP1 V No load on VPgate RsourceP VPgate source resistance 12.5 Ω IOUT=80mA RsinkP VPgate sink resistance 12.5 Ω IOUT=-80mA triseP VPgate rise time 50 ns C load=1.4nF tfallP VPgate fall time 50 ns C load=1.4nF tpwp(min) VPgate minimum pulse width (internally limited) 100 150 200 ns tdelayP PIN to Pgate delay time 300 ns mode=1 VPsen VPgate current sense voltage V PP1-0.85 V PP1-1.0 V PP1-1.15 V tshortP VPgate current sense off time 150 ns HV430

Negative High Voltage Output Symbol Parameter Min Typ Max Unit Conditions VNgate Output voltage swing V NN2 VNN1 V No load on VNgate RsourceN VNgate source resistance 15.0 Ω IOUT=80mA RsinkN VNgate sink resistance 15.0 Ω IOUT=-80mA triseN VNgate rise time 50 ns C load=1.0nF tfallN VNgate fall time 50 ns C load=1.0nF tpwn(min) VNgate minimum pulse width (internally limited) 100 150 200 ns tdelayN NIN to VNgate delay time 300 ns mode=1 VNsen VNgate current sense voltage V NN1+0.85 V NN1+1.0 V NN1+1.15 V tshortN VNgate current sense OFF time 150 ns Control Circuitry Symbol Parameter Min Typ Max Unit Conditions VIL Logic input low voltage 0 0.60 V V DD=5.0V VIH Logic input high voltage 2.7 5.0 V V DD=5.0V IINdn Input pull-down current 0.5 1 5 µAP IN, NIN, ENABLE Rup Input pull-up resistance 100 200 300 k Ω MODE VOL Logic output low voltage 0.50 V V DD=5.0V, IOUT=-0.5mA VOH Logic output high voltage 4.50 V V DD=5.0V, IOUT=0.5mA VRST(OFF) Reset voltage, device off 3.2 3.5 V V DD=5.0V VRST(ON) Reset voltage, device on 3.7 4.0 V V DD=5.0V VRST(HYS) Reset hysteresis voltage 0.3 V V DD=5.0V Ireset Reset pull-up current 7 10 13 µAV RESET=0-4.5V tRST(ON) RESET on delay 1.0 µs tRST(OFF) RESET off delay 1.0 µs tEN(ON) ENABLE on delay 50 100 150 µs tEN(OFF) ENABLE off delay 1.0 µs tFLT(HOLD) FAULT hold time 4 NIN/PIN ENABLE=1cycles tDB Deadband time 35 50 70 ns Mode=0, Rdb=5.6k Ω 105 140 175 ns Mode=0, Rdb=18k Ω tdelay(N-P) N-off to P-on transistion delay 300 ns Mode=0, Rdb<27k Ω tdelay(P-N) P-off to N-on transistion delay 300 ns Mode=0, Rdb<27k Ω ∆tdelay(N-P) Delay difference -80 0 80 ns Mode=1tdelayN(off) - tdelayP(on) ∆tdelay(P-N) Delay difference -80 0 80 ns Mode=1tdelayP(off) - tdelayN(on) HV430

Logic Inputs* Output NIN PIN mode EN RESET External N-Channel External P-Channel MOSFET MOSFET LL HH > V reset(on) OFF OFF LH H H > V reset(on) OFF ON HL H H > V reset(on) ON OFF HH H H > V reset(on) OFF OFF HX L H > V reset(on) OFF ON LX L H > V reset(on) ON OFF XX X L X OFF OFF XX X X < V reset(off) OFF OFF * Unused logic inputs should be connected to V DD or GND. Block Diagram and Application Circuit Ringer Output Rsense Rsense VDD Up Translator Down Translator Down Translator Up Translator P Driver N Driver Current Tr ip FAULT PIN NIN RESET De-glitcher DEADBAND ENABLE MODE VDD Control Logic VNN1 VPP1 SIG GND VPP2 Regulator VNN2 Regulator VDD Current Tr ip PWR GND +5V NC NC VPP1 VPP2 VPSEN VPGATE VNN1 VNN2 VNSEN VNGATE Note: PIN, NIN, and ENABLE are internally pulled low. MODE is internally pulled high. A Reset capacitor in the range of 1-10µF will yield a couple-second turn-on delay. Tantalum is recommended. 10µA resetclk HV430

Single-Control Mode Timing Dual-Control Mode Timing tPrise tN-Pdelay tP-Ndelay tNrise tN-Pdeadband NIN POUT NOUT tPfall tNfall tP-Ndeadband OFF ON OFF ON VNN1 VNN2 VPP1 VPP2 GND VDD tPrise tPdelay(on) tPdelay(off) tNrise tNfall tNdelay(on) tNdelay(off) PIN POUT NIN NOUT tPfall tPpulse(min) tNpulse(min) OFF ON OFF ON VNN1 VNN2 VPP1 VPP2 GND VDD GND VDD HV430

tEN(OFF)tEN(ON) Off Switching Off Switching Off Switching Off RESET Timing NIN /P IN POUT NOUT OFF ON OFF ON VNN1 VNN2 VPP1 VPP2 GND VDD RESET VRESET(ON) GND t RST(OFF)tRST(ON) Off Switching Off Switching Off Switching Off VRESET(OFF) HV430

Note: Nsense overcurrent shown. Psense operates identically. ENABLE or RESET 0 GND VDD VPP2 tFAULT(HOLD) ENABLE or RESET clears FAULT immediately GND VDD w/ext pull-up HV430

VPP1 Positive high voltage supply. VPP2 Positive gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should be connected between V PP2 and VPP1. VNN1 Negative high voltage supply. VNN2 Negative gate voltage supply. Generated by an internal linear regulator. A 25V, 100nF capacitor should be connected between V NN2 and VNN1. VDD Logic supply voltage. SGnd Low voltage logic ground. PGnd High voltage power ground. PIN Logic control input. When mode is high, logic input high turns ON the external high voltage P-channel MOSFET. Internally pulled low. NIN Logic control input. When mode is high, logic input high turns ON the external high voltage N-channel MOSFET. Internally pulled low. ENABLE Logic enable input. Logic high enables IC. Internally pulled low. MODE Logic mode input. 0=single-control; 1=dual-control. When MODE is high, N IN and PIN independently control N OUT and POUT, respectively. When MODE is low, NIN controls both outputs in a complementary manner. (See Truth Table) FAULT Logic output. Fault is at logic low when either current limit sense pin, V Psen or VNsen, is activated. Remains active until overcurrent condition clears or ENABLE=0 or RESET=0. RESET Power-on reset. A capacitor connected between this pin and ground determines the delay time between application of VDD and when the device outputs are enabled. Low leakage tantalum recommended. DEADBAND A resistor between this pin and ground sets the ‘break-before-make’ time between output transitions. Applicable only in single-control mode. For minimum deadtime, a 5.6k Ω resistor to ground should be used. For dual-input mode, tie to Vdd. VPgate Gate drive for external P-channel MOSFET. VNgate Gate drive for external N-channel MOSFET. VPsen Pulse by pulse over current sensing for P-Channel MOSFET. VNsen Pulse by pulse over current sensing for N-Channel MOSFET. Pin Configuration top view SOW 20 VDD Fault Mode PIN NIN Enable Reset Deadband SGND PGND V PP2 VPP1 VPSEN VPGATE N/C N/C V NGATE VNSEN VNN1 VNN2 HV430

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TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 12/13/010 ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.