HV3922 SUTEX | Alldatasheet
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❏ Processed with HVCMOS® technology ❏ 5V CMOS logic – low power dissipation ❏ DMOS output voltage up to 220V ❏ Low power level shifting – 5V to 220V ❏ Source current 1.7mA ❏ Output fault detection ❏ Latched data output Push-Pull Configuration Absolute Maximum Ratings Supply Voltage, VCC -0.5V to +7.0V Logic Input Voltage -0.3V to VCC + 0.3V Supply Voltage V LL -5.0V Supply Voltage VPP +230V Max Power Dissipation 0.8W Junction Temperature +150 °C Storage Temperature Range -65 °C to +150 °C Operating Temperature Range -55 °C to +125 °C Lead Soldering Temperature for 10 Seconds +300 °C * VN2222NC is an N-channel DMOS FET quad array recommended for use in conjunction with HV39 outputs to form four 220V push-pull outputs. Each of the four devices has a max R DS(ON) of 1.25Ω, min ID(ON) of 5.0 amps, and BVDSS of 220V. 12/13/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liabi lity to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to c hange without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most curre nt databook or to the Legal/Disclaimer page on the Supertex website.
Symbol Parameter Min Max Units Conditions ICCQ Maximum Quiescent VCC Supply Current 1.0 mA V CC = 5.5V All ouputs open ILLQ Maximum Quiescent VLL Supply Current 4.0 mA V LL= -3.5V DRV(N) high or low IPPQ Maximum Quiescent VPP Supply Current 100 µAV PP = 220V PD(N) high or low IIH High-level logic current 10 µAH = VCC IIL Low-level logic current 10 µAL = 0V VFH Minimum high-level logic output voltage 4.4 V V CC = 4.5V, IOH = 20µA (fault detect) VFL Maximum low-level logic output voltage 0.1 V V CC = 5.5V, IOL =-20µA (fault detect) VDH Minimum PD(N) high-level output voltage 198 V V PP = 203V, IOH=1.7mA VDH Minimum DRV(N) high-level output voltage 4 V V CC = 4.5V, IOH=100µA VDL Maximum DRV(N) low-output voltage -2.3 V V LL = -2.5V, IDL = -500µA VTH(min) Minimum fault threshold for PD(N) output high 0.5 x V PP VP D(N) = HIGH, OE = VCC fault VTH(max) Maximum fault threshold for PD(N) output high 0.85 x V PP VP D(N) = HIGH, OE = VCC fault VTL(min) Minimum fault threshold for PD(N) output Hi-Z V (PDN) = 0V V P D(N) = Hi-Z, OE = VCC VTL(max) Maximum fault threshold for PD(N) output Hi-Z V (PDN) = 25 V P D(N) = Hi-Z, OE = VCC AC Characteristics (over recommended operating conditions unless noted) Symbol Parameter Min Max Units Conditions tWCS Minimum CS pulse to latch data 100 ns V CC= 4.5V, ENA = 0V tWENA Minimum ENA pulse width to latch data 100 ns V CC= 4.5V, CS = 0V tWOE OE pulse width 10 50 µsV CC= 4.5V, OE = 0V, VPP = 220V PD(N) LOAD = 20K to GND 16 50 µsV PP = 220V, PD(N) LOAD = 20K and 3000pF to GND TT Input transition rise and fall times 0 200 ns V CC= 4.5V TSU1 Minimum set-up time DN and CS to ENA 150 ns V CC= 4.5V TSU2 Minimum set-up time ENA to OE falling edge 150 ns V CC= 4.5V TH Minimum hold time 5 ns V CC= 4.5V CIN Maximum input capacitance 10 pF Not tested, reference only TO P D(N) transition time from OE low to 1 50 µsV PP = 220V PD(N) high/low PD(N) output loaded by 20K ohms & 3000pF to GND Electrical Characteristics (over recommended operating conditions unless noted) DC Characteristics HV3922
Recommended Operating Conditions Symbol Parameter Min Max Units VCC Logic Supply Voltage 4.5 5.5 V VIN DC Logic Input Voltage 0 V CC V VLL VLL Supply Voltage -3.5 -2.5 V VPP VPP Supply Voltage 200 220 V IPD(N)H High-State Continuous PD(N) Source Current 1.7 mA TA Ambient Operating Temp -55 +125 °C CL D RV(N) Load Capacitance 0 0.006 µF Notes: 1.VPP rise time (dv/dt) should be less than 50V/ µS. 2.Power-up sequence should be the following: A) Connect ground; B) Apply V CC; C) Apply V LL; D) Apply V PP; E) Set all inputs to a known state. Power-down sequence should be the reverse of the above. Function Table Input Output Data V TH Internal CS ENA OE D (N) Level2 Latch Q(N) P D(N) DRV(N) Fault HX HX Pass Previous State Previous State Previous State VFH XH HX Pass Previous State Previous State Previous State VFH LL HH Pass Set Previous State Previous State VFH LL HL Pass Reset Previous State Previous State VFH LL H>L H P/F Set VDH VDL VFH LL H>L L P/F Reset HI-Z VDH VFH HX H>L X Previous State P/F Set VDH VDL VFH P/F Reset HI-Z VDH VFH XH H>L X Previous State Pass Set VDH VDL VFH Pass Reset HI-Z VDH VFH XX HX Fail — HI-Z VDL VFL (At Power Up) XX V IH X P/F Set VDH VDL VFH Notes: 1. X indicates “Don’t Care” input state (L or H). 2. The output threshold is internally tested for each P D(N) output; the pass condition occurs when OE = H and: A) P D(N) driving high with output > VTH (MAX), or may occurs if PD(N) driving high and output > VTH (MIN) and < VTL (MAX). OR B) P D(N) driving Low with output < VTH (MIN), or may occur if PD(N) driving low and output < VTH (MAX) and < VTL (MIN). The fail condition occurs when OE = H and conditions for “pass” are not satisfied. 3. Fault output = V FL indicates a fault has been detected in at least one of the PD(N) output loads when OE = H. All other outputs shall function normally when a fault condition has been detected for one of the outputs. The Fault output shall remain in the low state, regardless of the state of the output which initiated the fault status, until the next falling edge of OE. Whenever OE = L, the Fault output is forced to VFH, and the fault latch is reset. If the fault condition persists, the fault response repeats each time the OE input is set to H. 4. H>L indicates falling edge (H to L). 5. HI-Z indicates no current is sourced to output P D(N). 6. P/F indicates “Pass” or “Fail” fault threshold conditions.
and CS 10% 10% tWCS 90% 90% tSU1 90% 10% 10% TH tWENA TT 90% 10% TT 10% tWOE 90% 10% tSU2 DATA HIGH ENA OE PD(N) DRV(N) tOH VPP VCC VLL GND DO Latch Q Set FF Q Set CLK Latch Q Set FF Q Set CLK Latch Q Set FF Q Set CLK Latch Q Set FF Q Set CLK OE ENA CS V PP Voltage Sense Gate Control Circuit Drive Circuit Drive Circuit Drive Circuit Power-Up Circuit Drive Circuit Fault 0 PD0 DRV0 PD1 DRV1 PD2 DRV2 PD3 DRV3 Fault Timing Diagram Functional Block Diagram
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 12/13/010 ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. HV3922 25 19 24 23 22 21 20 5 116789 1 0 Pin Configurations Package Outline