HV3527

HV3527 SUTEX | Alldatasheet

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Technical content

Features

■■ HVCMOS® technology ■■ Output voltages up to 275V ■■ Low power level shifting ■■ Shift register speed 6MHz @ VDD = 5V ■■ Latched data outputs ■■ Output polarity and blanking ■■ CMOS compatible inputs ■■ Forward and reverse shifting options Absolute Maximum Ratings1 Supply voltage, VDD -0.5V to +6V Supply voltage, VPP VDD to 300V Logic input levels -0.5V to VDD +0.5V Ground current2 1.5A High voltage supply current2 1.3A Continuous total power dissipation3 1200mW Operating temperature range 0°C to +70°C Storage temperature range -65°C to +150°C Notes: 1. All voltages are referenced to GND. 2. Connection to all power and ground pads is required. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25°C ambient derate linearly to 85°C at 15mW/°C. HV3527

Symbol Parameter Min Typ Max Units Conditions fCLK Clock Frequency 6 MHz tW Clock Width High and Low High 83 ns tSU Data Setup Time Before Clock Rises 35 ns tH Data Hold Time After Clock Rises 30 ns tWLE Width of Latch Enable Pulse 80 ns tDLE LE Delay Time Rising Edge of Clock 35 ns tSLE LE Setup Time Before Rising Edge of Clock 40 ns tON , tOFF Time from Latch Enable to HVOUT 1.5 µsC L = 20pF tDHL Delay Time Clock to Data High to Low 110 ns C L = 20pF tDLH Delay Time Clock to Data Low to High 160 ns C L = 20pF tr, tf All Logic Inputs 5 ns Notes: 1. Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec. 2. AC Characteristics are guaranteed only under VDD = 5V. Symbol Parameter Min Typ Max Units VDD Logic supply voltage 4.5 5.0 5.5 V VPP High voltage supply 60 275 V VIH High-level input voltage V DD -0.9 V DD V VIL Low-level input voltage 0 0.9 V TA Operating free-air temperature 0 +70 °C Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply V DD . 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP . Power-down sequence should be the reverse of the above. Electrical Characteristics (over recommended operating conditions unless noted) Symbol Parameter Min Typ Max Units Conditions IDD VDD Supply Current 25 mA f CLK = 6MHz, fDATA = 3MHz LE = LOW IDDQ Quiescent VDD Supply Current 200 µA All V IN = 0V or VDD IPP High Voltage Supply Current 0.50 mA V PP = 275V All outputs high 0.50 mA V PP = 275V All outputs low IIH High-Level Logic Input Current 10 µAV IH = VDD IIL Low-Level Logic Input Current -10 µAV IL = 0V VOH High-Level Output HV OUT 200 V V PP = 275V, IHVOUT = -1mA Data Out V DD -1V V ID OUT = -100µA VOL Low-Level Output HV OUT 10 V IHV OUT = 1mA, VDD = 5V Data Out 1.0 V ID OUT = 100µA VOC HV OUT Clamp Voltage V PP +1.5 V I OL = +5mA -1.5 V I OL = -5mA DC Characteristics Recommended Operating Conditions AC Characteristics1,2 (For VDD = 5V; VPP = 275V, TA = 25°C)

Data Valid50% 50%Data Input Clock (DIOA/DIOB) 50% 50% 50% tSU tH tWL tWH 50% 50% tDLH tDHL 50% tWLEtDLE tSLE 50% 50% tON 10% HV OUT w/ S/R HIGH 90% 90%10% tOFF VIH VIL VIH VIL VOH VOL VOH VOL VIH VOL VOH VOL VOH VOL Data OUT VDD Input GND VPP GND HV OUT Logic Inputs GND Data Out Logic Data Output High Voltage Outputs VDD Input and Output Equivalent Circuits Switching Waveforms

60 Additional

64 Latches

VBIAS Voltage V PP Operating Voltage VBIAS = 0V or VPP VPP = 200V VBIAS =V PP = 275V Functional Block Diagram VPP can be used with a voltage divider to get VBIAS or a separate voltage supply can be used for VBIAS. R 2 VPP VBIAS R 1 Inputs Outputs Function Shift Reg HV Outputs Data Out 12 … 64 1 2 … 64 * All on X X X L L X * * … *HH … H* All off X X X L H X * * … *L L … L* Load S/R H or L ↑ L H H X H or L * … ** * … ** D IOA ↑ XXXL Q n→ Q n-1 —D IOB D IOB ↑ XXXH Q n→ Q n+1 —D IOA Notes: H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition, ↓ = high-to-low transition. * = dependent on previous stage’s state before the last CLK or last LE high. Data CLK LE BL POL DIR Load/Store Data in Latches Transparent Latch mode I/O Relation Function Table VBIAS Table 2 V

2H V OUT 42/23 42 HV OUT 2/63 3H V OUT 43/22 43 HV OUT 3/62 4H V OUT 44/21 44 HV OUT 4/61 5H V OUT 45/20 45 HV OUT 5/60 6H V OUT 46/19 46 HV OUT 6/59 7H V OUT 47/18 47 HV OUT 7/58 8H V OUT 48/17 48 HV OUT 8/57 9H V OUT 49/16 49 HV OUT 9/56

10 HV OUT 50/15 50 HV OUT 10/55

11 HV OUT 51/14 51 HV OUT 11/54

12 HV OUT 52/13 52 HV OUT 12/53

13 HV OUT 53/12 53 HV OUT 13/52

14 HV OUT 54/11 54 HV OUT 14/51

15 HV OUT 55/10 55 HV OUT 15/50

16 HV OUT 56/9 56 HV OUT 16/49

17 HV OUT 57/8 57 HV OUT 17/48

18 HV OUT 58/7 58 HV OUT 18/47

19 HV OUT 59/6 59 HV OUT 19/46

20 HV OUT 60/5 60 HV OUT 20/45

21 HV OUT 61/4 61 HV OUT 21/44

22 HV OUT 62/3 62 HV OUT 22/43

23 HV OUT 63/2 63 HV OUT 23/42

24 HV OUT 64/1 64 HV OUT 24/41

25 V PP 65 HV OUT 25/40

26 D IOA 66 HV OUT 26/39

27 N/C 67 HV OUT 27/38

28 N/C 68 HV OUT 28/37

29 BL 69 HV OUT 29/36

30 POL 70 HV OUT 30/35

31 V DD 71 HV OUT 31/34

32 DIR 72 HV OUT 32/33

33 V BIAS 73 HV OUT 33/32

34 GND 74 HV OUT 34/31

35 N/C 75 HV OUT 35/30

36 N/C 76 HV OUT 36/29

37 CLK 77 HV OUT 37/28

38 LE 78 HV OUT 38/27

39 D IOB 79 HV OUT 39/26

40 V PP 80 HV OUT 40/25

Note: Pin designation for DIR = H/L Example: for DIR = H, Pin 1 is HVOUT 41 for DIR = L, Pin 1 is HVOUT 24 Pin Configurations Package Outline