HV3418

HV3418 SUTEX | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 5

Technical content

Features

❏ HVCMOS® technology ❏ Output voltages up to 180V ❏ Low power level shifting ❏ Shift register speed: 6MHz @ VDD = 5V 12MHz @ VDD = 12V ❏ Latched data outputs ❏ Output polarity and blanking ❏ CMOS compatible inputs ❏ Forward and reverse shifting options Absolute Maximum Ratings1 Supply voltage, VDD -0.5V to +15V Supply voltage, VPP VDD to +200V Logic input levels -0.5V to V DD +0.5V Ground current2 1.5A High voltage supply current2 1.3A Continuous total power dissipation3 Ceramic 1900mW Plastic 1200mW Operating temperature range Ceramic -55 °C to +125°C Plastic -40 °C to +85°C Storage temperature range -65 °C to +150°C Notes: 1. All voltages are referenced to GND. 2. Connection to all power and ground pads is required. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25 °C ambient derate linearly to maximum operating temperature at 20mW/°C for plastic and at 31.7mW/°C for ceramic.

Symbol Parameter Min Typ Max Units VDD Logic supply voltage V DD = 5V 4.5 5.0 5.5 V VDD =12V 10.8 12.0 13.2 V VPP High voltage supply 60 180 V VIH High-level input voltage V DD -0.9 V DD V VIL Low-level input voltage 0 0.9 V TA Operating free-air temperature Plastic -40 +85 °C Ceramic -55 +125 Notes: Power-up sequence should be the following: 1. Connect ground. 4. Apply V PP. 2. Apply V DD.5 . The VPP should not drop below VDD or float during operation. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. Power-down sequence should be the reverse of the above. Symbol Parameter Min Typ Max Units Conditions fCLK Clock Frequency 12(6) MHz tW Clock Width High and Low High 40(83) ns tSU Data Setup Time Before Clock Rises 25(35) ns tH Data Hold Time After Clock Rises 10(30) ns tWLE Width of Latch Enable Pulse 62(80) ns tDLE LE Delay Time Rising Edge of Clock 25(35) ns tSLE LE Setup Time Before Rising Edge of Clock 30(40) ns tON, tOFF Time from Latch Enable to HVOUT 1(1.5) µsC L = 20pF tDHL Delay Time Clock to Data High to Low 50(110) ns C L = 20pF tDLH Delay Time Clock to Data Low to High 75(160) ns C L = 20pF tr, tf All Logic Inputs 5 ns Notes: 1. Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec. 2. AC Characteristics are guaranteed only under V DD = 12V and VDD = 5V. Electrical Characteristics (over recommended operating conditions unless noted) Symbol Parameter Min Typ Max Units Conditions IDD VDD Supply Current 25 mA f CLK = 12MHz, fDATA = 12MHz LE = LOW IDDQ Quiescent VDD Supply Current 200 µA All VIN = 0V or VDD IPP High Voltage Supply Current 0.50 mA V PP = 180V All outputs high 0.50 mA V PP = 180V All outputs low IIH High-Level Logic Input Current 10 µAV IH = VDD IIL Low-Level Logic Input Current -10 µAV IL = 0V VOH High-Level Output HV OUT 155 V V PP = 180V, IHVOUT = -5mA Data Out V DD -1V V ID OUT = -100µA VOL Low-Level Output HV OUT 25 V V PP = 180V, IHVOUT = +5mA Data Out 1.0 V ID OUT = +100µA VOC HVOUT Clamp Voltage V PP +1.5 V I OL = +5mA -1.5 V I OL = -5mA DC Characteristics Recommended Operating Conditions AC Characteristics1,2 (For VDD = 12V: values in parentheses are for VDD = 5V; VPP = 180V, TA = 25°C) HV3418

Data Valid50% 50%Data Input Clock DIO/DOI 50% 50% 50% tSU tH tWL tWH 50% 50% tDLH tDHL 50% tWLEtDLE tSLE 50% 50% tON 10% HVOUT w/ S/R HIGH 90% 90%10% tOFF VIH VIL VIH VIL VOH VOL VOH VOL VIH VOL VOH VOL VOH VOL VDD Input GND VPP GND HVOUT Logic Inputs GND Data Out Logic Data Output High Voltage Outputs VDD Input and Output Equivalent Circuits Switching Waveforms

60 Additional

64 Latches

Function Shift Reg HV Outputs Data Out 12 … 64 1 2 … 64 * All on X X X L L X * * … *HH … H* All off X X X L H X * * … *L L … L* DIOA ↑ XXXL Q n→ Qn-1 —D IOB DIOB ↑ XXXH Q n→ Qn+1 —D IOA Notes: H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition, ↓ = high-to-low transition. * = dependent on previous stage’s state before the last CLK or last LE high. Data CLK LE BL POL DIR Load/Store Data in Latches Transparent Latch mode Function Table I/O Relation Functional Block Diagram

Pin Configurations Package Outline HV34 Pin Function Pin Function 1H V OUT 41/24 41 HV OUT 1/64 2H V OUT 42/23 42 HV OUT 2/63 3H V OUT 43/22 43 HV OUT 3/62 4H V OUT 44/21 44 HV OUT 4/61 5H V OUT 45/20 45 HV OUT 5/60 6H V OUT 46/19 46 HV OUT 6/59 7H V OUT 47/18 47 HV OUT 7/58 8H V OUT 48/17 48 HV OUT 8/57 9H V OUT 49/16 49 HV OUT 9/56

10 HV OUT 50/15 50 HV OUT 10/55

11 HV OUT 51/14 51 HV OUT 11/54

12 HV OUT 52/13 52 HV OUT 12/53

13 HV OUT 53/12 53 HV OUT 13/52

14 HV OUT 54/11 54 HV OUT 14/51

15 HV OUT 55/10 55 HV OUT 15/50

16 HV OUT 56/9 56 HV OUT 16/49

17 HV OUT 57/8 57 HV OUT 17/48

18 HV OUT 58/7 58 HV OUT 18/47

19 HV OUT 59/6 59 HV OUT 19/46

20 HV OUT 60/5 60 HV OUT 20/45

21 HV OUT 61/4 61 HV OUT 21/44

22 HV OUT 62/3 62 HV OUT 22/43

23 HV OUT 63/2 63 HV OUT 23/42

24 HV OUT 64/1 64 HV OUT 24/41

25 V PP 65 HV OUT 25/40

26 D IOA 66 HV OUT 26/39

27 N/C 67 HV OUT 27/38

28 N/C 68 HV OUT 28/37

29 BL 69 HV OUT 29/36

30 POL 70 HV OUT 30/35

31 V DD 71 HV OUT 31/34

32 DIR 72 HV OUT 32/33

33 LGND 73 HV OUT 33/32

34 OGND 74 HV OUT 34/31

35 N/C 75 HV OUT 35/30

36 N/C 76 HV OUT 36/29

37 CLK 77 HV OUT 37/28

38 LE 78 HV OUT 38/27

39 D IOB 79 HV OUT 39/26

40 V PP 80 HV OUT 40/25

Note: Pin designation for DIR = H/L Example: for DIR = H, Pin 1 is HV OUT41 for DIR = L, Pin 1 is HVOUT24 HV3418

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 12/13/010 ©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.