HV301

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Document overview

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Technical content

Features

❑ ±10V to ±90V Operation ❑ Built-in “normally on” turn-on clamp eliminates components ❑ UV/OV Lock Out & Power-on-Reset(POR) for Debouncing ❑ Sense resistor programmed circuit breaker ❑ Programmable circuit breaker holdoff ❑ Inrush control using either: i) servo or ii) feedback cap ❑ Feedback to Ramp pin means no Gate Clamp needed ❑ Application solution for input voltage step (diode “ORing”) ❑ Programmable Auto-Retry (tens of seconds if desired) ❑ Auto-Retry or Latched Operation ❑ Enable through Open Drain interface to UV or OV ❑ Low Power, <0.6mA , <0.4mA Sleep Mode ❑ PWRGD Flag ❑ Small SOIC-8 Package

Applications

❑ -48V Central Office Switching ❑ -24V Cellular and Fixed Wireless Systems ❑ -24V PBX Systems ❑ Line Cards ❑ -48V Powered Ethernet for VoIP ❑ Distributed Power Systems ❑ Power Supply Control ❑ +48V Storage Networks ❑ Electronic Circuit Breaker General Description The Supertex HV301 and HV311 Hotswap Controllers provide control of power supply connection during insertion of cards or modules into live backplanes. They may be used in systems where active control is implemented in the negative lead of supplies ranging from ±10V to ±90V. During initial power application the gate of the external pass device is clamped low to suppress contact bounce glitches by a “normally on” circuit which does not require initialization of the IC. Thereafter the UV/OV supervisors and power-on-reset work together to suppress gate turn on until mechanical bounce has ended. The HV301/311 then control the current inrush limit to a programmed level using one of two possible methods, i) servo control or ii) a drain to ramp capacitor. The above methods eliminate the need for extra hold-off or current limiting compo- nents. The devices also include an electronic circuit breaker, programmed by a sense resistor. After the load capacitance has fully charged, the HV301/311 will transition into a low power mode, and enable the open drain PWRGD. In low power mode the HV301/311 continues to moni- tor the input voltage and monitor the current level. If a load fault occurs, the electronic circuit breaker will trip, the pass element will be turned off, and the PWRGD will return to an (continued on Page 21) VDD UV OV VEE SENSE GATE -48V 12.5mΩ 487kΩ 6.81kΩ 9.76kΩ IRF530 Cload +5V HV301/ HV311 COM DC/DC PWM CONVERTER GND PWRGD / PWRGD ENABLE / ENABLE RAMP 10nF -48V Notes: 1. Undervoltage Shutdown (UV) set to 35V. 2. Overvoltage Shutdown (OV) set to 65V. 3. Current Limit set to -1A. 4. CB set to 8A. Typical Application Circuit 0.75nF Hotswap, Controllers with Circuit Breaker (Negative Supply Rail) HV301 HV311 Demo Kit Available

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VEE reference to VDD pin +0.3V to -100V VPWRGD referenced to VEE Voltage -0.3V to +100V VUV and VOV referenced to VEE Voltage -0.3V to +12V Operating Ambient Temperature -40 °C to +85°C Operating Junction Temperature -40 °C to +125°C Storage Temperature Range -65 °C to +150°C Pin Description PWRGD – The Power Good Output Pin is held inactive on initial power application and will go active when the external MOSFET is fully turned on. This pin may be used as an enable control when connected directly to a PWM power module. OV – This OverVoltage (OV) sense pin, when raised above its high threshold will immediately cause the GATE pin to be pulled low. The GATE pin will remain low until the voltage on this pin falls below the low threshold limit, initiating a new start-up cycle. UV – This UnderVoltage (UV) sense pin, when below its low threshold limit will immediately cause the GATE pin to be pulled low. The GATE pin will remain low until the voltage on this pin rises above the high threshold limit, initiating a new start-up cycle. V EE – This pin is the negative terminal of the power supply input to the circuit. VDD – This pin is the positive terminal of the power supply input to the circuit. RAMP – This pin provides a current output so that a timing ramp voltage is generated when a capacitor is connected. GATE – This is the Gate Driver Output for the external N- Channel MOSFET. SENSE – The current sense resistor connected from this pin to VEE Pin programs the circuit breaker trip limit. General Description, cont’d. PWRGD Logic ledoMn oitidnoCD GRWP 103VH )ydaeRtoN(EVITCANI0 V EE )ydaeR(EVITCA1 Z IH 113VH )ydaeRtoN(EVITCANI1 Z IH )ydaeR(EVITCA0 V EE inactive state. Thereafter a programmable auto-retry timer will hold the device off to allow the pass element to cool before resetting and restarting. The auto-retry can be disabled using a single resistor if desired. The HV301/HV311 includes a current mode servo-circuit which can be used as a return to limit during input voltage steps such as would be seen in a diode “ORed” situation when power switches back to regulated supply from battery operation. The HV301/HV311 allow independent programming of the trigger level of this phenomenon so that it may be set at a different level to the current limit level if desired. Under all circumstances the maximum servo period is limited to 100ms to protect the pass element. Pinout PWRGD (HV301) PWRGD (HV311) OV UV VEE VDD RAMP GATE SENSE

Ordering Information

5.00ms/div Waveforms Drain 50V/div VIN 50V/div Gate 5.00V/div Iinrush 500mA/div

Insertion into Hot Backplanes Telecom, data networks and some computer applications re- quire the ability to insert and remove circuit cards from systems without powering down the entire system. All circuit cards have some filter capacitance on the power rails, which is especially true in circuit cards or network terminal equipment utilizing distributed power systems. The insertion can result in high inrush currents that can cause damage to connector and circuit cards and may result in unacceptable disturbances on the system backplane power rails. The HV301 and HV311 are designed to facilitate the insertion of these circuit cards or connection of terminal equipment by eliminating these inrush currents and powering up these circuits in a controlled manner after full connector insertion has been achieved. The HV301 or HV311 is intended to provide this function on supply rails in the range of ±10 to ±90 Volts. Description of Operation During initial power application, a unique proprietary circuit holds off the external MOSFET, preventing an input glitch while an internal regulator establishes an internal operating voltage of approximately 10V. Until the proper internal voltage is achieved all circuits are held reset, the PWRGD output is inactive and the gate to source voltage of the external MOSFET is clamped low. Once the internal under voltage lock out (UVLO) has been satisfied, the circuit checks the input supply undervoltage (UV) and overvoltage (OV) sense circuits to ensure that the input voltage is within programmed limits. These limits are determined by the selected values of resistors R1, R2 and R3, which form a voltage divider. Assuming the above conditions are satisfied and while continu- ing to hold the PWRGD output inactive and the external MOSFET GATE voltage low, the current source feeding the RAMP pin is turned on. The external capacitor connected to it begins to charge, thus starting an initial time delay determined by the value of the capacitor. During this time if the OV or UV limits are exceeded, an immediate reset occurs and the capacitor con- nected to the RAMP pin is discharged. When the voltage on the RAMP pin reaches an internally set threshold voltage, the gate drive circuit begins to turn on the external MOSFET. In servo mode, once the gate threshold is reached, the resulting output current generates a voltage drop on the sense resistor connected between the SENSE and V EE pins, causing a decrease in the available current charging the capacitor on the RAMP pin. This continuous feedback mecha- nism allows the output current to rise inverse exponentially over a period of a few hundred microseconds to the sense resistor programmed current limit set point. When the voltage drop on the sense resistor reaches 50mV the RAMP pin current is reduced to zero and the voltage on the Vbg C C C UV OV Logic Regulator & POR VIN PWRGD = HV301 PWRGD = HV311 ~9.8V RAMP 2Vbg gm SENSE 10µA Transconductor D I S A B L E P U L L H I G H VDD 1 : 2 buffer mirror GATE Latch High Sleep Clamp Mechanism Transconductor UVLO VEE

RAMP pin will be fixed, indicating that the circuit is in current limit mode. Depending on the value of the load capacitor and the programmed current limit, charging may continue for some time, but may not exceed a nominal 100ms preset time limit. Once the load capacitor has been charged, the output current will drop, reducing the voltage on the SENSE pin, which in turn will increase the RAMP pin current, thus causing the voltage on the capacitor connected to the RAMP pin to continue rising, thereby providing yet another programmed delay. If due to output over- load conditions during startup, PWRGD does not achieve an active state within 100ms or the circuit breaker is tripped, the circuit is reset, pulling down the GATE to V EE, discharging the capacitor connected to the RAMP pin, changing PWRGD to an inactive state. A timeout or circuit breaker fault will initiate an auto-retry if enabled. On the other hand, in feedback capacitor mode, a current source of 10 µA from the RAMP pin limits the dv/dt of the feedback capacitor which, in turn, programs Inrush according to Inrush ~ 10 µA•Cload/C2. (See Programming Inrush and I CB for accurate formula on page 6.) When the ramp voltage is within 1.2V of the regulated internal supply voltage, the controller will force the GATE terminal to a nominal 10V, the PWRGD pin will change to an active state, the circuit breaker supervisor is enabled and the circuit will transition to a low power sleep mode. When the voltage on the SENSE pin rises to 100mV, indicating an over current condition, the circuit breaker will trip in less than 5µs. This time may be extended by the addition of external components. At any time during the start up cycle or thereafter, crossing the UV and OV limits (including hysteresis) will cause an immediate reset of all internal circuitry. When the input supply voltage returns to a value within the programmed UV and OV limits a new start up sequence will be initiated. Functional Description, cont’d. Design Information Setting UnderVoltage and OverVoltage Shut Down The UV and OV pins are connected to comparators with nominal 1.21V thresholds and 100mV of hysteresis (1.21V ± 50mV). They are used to detect under voltage and over voltage condi- tions at the input to the circuit. Whenever the OV pin rises above its high threshold (1.26V) or the UV pin falls below its low threshold (1.16V) the GATE voltage is immediately pulled low, the PWRGD pin changes to its inactive state and the external capacitor connected to the RAMP pin is discharged. Calculations can be based on either the desired input voltage operating limits or the input voltage shutdown limits. In the following equations the shutdown limits are assumed. The undervoltage and overvoltage shut down thresholds can be programmed by means of the three resistor divider formed by R1, R2 and R3. Since the input currents on the UV and OV pins are negligible the resistor values may be calculated as follows: UV V V RR RR R OV V V R RR R OFF UVL EEUV off OFF OVH EEOV off == = × + == = × ++ 11 6 23 123 12 6 3 123 Where |VEEUV(off)| and |VEEOV(off)| relative to VEE are Under & Over Voltage Shut Down Threshold points. If we select a divider current of 100 µA at a nominal operating input voltage of 50 Volts then RR R123 50 100 500++= µ =V A kΩ From the second equation for an OV shut down threshold of 65V the value of R3 may be calculated. OV R R OFF == × = × = 12 6 65 3 500 3 12 6 500 65 96 9 . k .k .k Ω Ω Ω The closest 1% value is 9.76k Ω. From the first equation for a UV shut down threshold of 35V the value of R2 can be calculated. UV RR R OFF == ×+( ) = × − = 11 6 35 2 3 500 2 11 6 500 35 97 6 68 1 . .. k k kk Ω Ω ΩΩ The closest 1% value is 6.81k Ω. Then RR R1 500 2 3 483= −− =kkΩΩ The closest 1% value is 487k Ω.

From the calculated resistor values the OV and UV start up threshold voltages can be calculated as follows: UV V V RR RR R OV V V R RR R ON UVH EEUV on ON OVL EEOV on == = × + == = × ++ 12 6 23 123 11 6 3 123 Where |VEEUV(on)| and |VEEOV(on)| are Under & Over Voltage Start Up Threshold points relative to V EE. Then V RR R RR V V RR R R V EEUV on EEUV on EEOV on EEOV on . .. .. . . .. =× ++ =× ++ + = =× ++ =× ++ 12 6 123 12 6 487 6 81 9 76 68 1 97 6 38 29 11 6 123 11 6 487 6 81 9 76 97 6 kkk kk V And kkk k ΩΩΩ ΩΩ ΩΩΩ Ω == 59 85.V Therefore, the circuit will start when the input supply voltage is in the range of 38.29V to 59.85V. Design Information, cont’d. Undervoltage/Overvoltage Operation Programming Inrush and ICB (Circuit Breaker) Method 1: Inrush independent of I CB Max Vt of a typical power FET GND VIN Pass Transistor OFF ON UVOFF UVON OVOFF OVON VSENSE + K – 2.5µA 7.5µA 10µA 10V 10n 0µA 0µA RAMP GATE 7.5µA Vgs Cgs Cgd – + inrush Rsense=12.5mΩ Cdb (DRAIN) Cload=100µF Vin dv df on Cramp constant during limiting so no current flowing into cap gm(Vgs-Vt) VSENSE VSENSE 10V 10n=Cramp RAMP terminal GATE Termial 1 : 2 Isink 10µA Internal Circuitry mirror 0.75nF Rsense Vsense Cload 48V10µA 1. Choose circuit breaker trip point eg. 8A as follows Rsense = Choose inrush level, for example Inrush =1A 3. Calculate Isink Inrush*Rsense 2.5 A 4. Calculate C discharge limit = 10 A -Isink = 7.5 A (typical) = iC 4a. Adjust for Auto-retry disable, if used Vt R e.g. 4V 2.5M = 1.6 A e.g. iC =10 A -Isink -1.6 A max disable 100 100 8 12 5 11 2 5 mV I mV m k Am k CB == × =µ µµ ≅ Ω µ ⇒ µµ Ω Ω Ω Ω In this example we assume AutoIn this example we assume Auto-retry is enabled so ignore 1.6 A, iC = 10 A -Isink = 7.5 A 5. Note: i = C iC = C Inrush = C Note V is fixed and V is constant during limiting across C = across C (as they share a common node and their other terminals are fixed during inrush) Inrush = by conservation of charge on RAMP Node iC = 7.5 A Inrush = . 22 load IN RAMP load 2 µ ∴ µµ = ⇒ × µ dv dt dv dt dv dt dv dt dv dt iC C Inrush C iC C C AC load load load CC AC Inrush An F A load 75 100 ⇒ µ× = µ× C= . = 750pF = 0.75nF Note that RAMP is protected by AC divider and Gate is clamped internally.

The timing functions are defined by the following equations: t C I tV C I tt t t C g I I R R tV C I tV V C I START RAMP RAMP TH GS th RAMP RAMP POR START TH RISE RAMP fs RAMP LIMIT SENSE FB LIMIT IN LOAD LIMIT PWRGD INT GS RAMP RAMP = −−() ()LIMIT Timing (Servo Mode) Design Information, cont’d. Programming Inrush and ICB, continued: Method 2: Inrush = 1/2 I CB (Servo Mode) i) start with 2nF from gate to source ii) increase to 10nF if needed iii) add 1k series resistor from gate to capacitor if needed Capacitor and/or compensation resistor will reduce peaking GND -48V VIN IIN tSTART contact bounce ILIM PWRGD VUVL tRISE tPWRGD VGATE Initialization Limiting Full On VGATE VOUT tLIM tTH VRAMP VRAMP VGATE inactive active VOUT VIN VGS(th) VGS(lim) VEE tPOR 90% 1. Choose I = 100mV R e.g. 2A R = 50m 2. Inrush = 50mv R , e.g. 50mV 50m =1A 3. Add compensation components from gate to drain if necessary to reduce peaking. CB SENSE SENSE SENSE , ⇒Ω Ω

Start up Overload Protection Start up must be achieved within a nominal 100ms as indicated by the PWRGD pin transition to the active state or the circuit will reset and an automatic restart will initiate. If there is an output overload or short circuit during start up, the circuit will be in current limit for the 100ms time limit (in servo mode). In feedback capacitor mode the circuit breaker will shutdown the pass FET before 100ms. Circuit Breaker The circuit breaker will trip in less than 5µs when the voltage on the SENSE pin reaches a nominal 100mV. A resistor in series with the SENSE pin and a capacitor connected between the SENSE and V EE pins may be added to delay the rate of voltage rise on the SENSE pin, thus permitting a current overshoot and delaying Circuit Breaker activation. Automatic Restart The automatic restart delay time is directly proportional to the capacitance at the RAMP pin. Automatic restart sequence is activated whenever the 100ms timeout is reached during start up or the circuit breaker is tripped. These equations assume that the load is purely capacitive and the following definitions apply. CRAMP is the external capacitor connected to the RAMP pin. IRAMP is the output current from the RAMP pin, nominally 10µA, when the voltage drop on R SENSE resistor is zero. VINT is the internally regulated supply voltage and can range from 8.5V to 12V. VGS(th) is the gate threshold voltage of the external pass transistor and may be obtained from its datasheet. VGS(limit) is the external pass transistor gate-source voltage required to obtain the limit current. It is dependent on the pass transistor’s characteristics and may be obtained from the transfer characteristics on the transistor datasheet. gfs is the transconductance of the external pass transistor and may be obtained from its datasheet. RFB is the internal feedback resistor and is nominally 5k Ω. ILIMIT is the load current when the voltage drop on the R SENSE resistor is 50mV. These equations may be used to calculate the minimum value of CRAMP for the most critical system performance characteristics. For maximum contact bounce duration protection choose a value for tPOR and use the following equation: C tI VRAMP POR RAMP GS th = × +24. () If control of PWRGD active delay is the critical system param- eter, then choose a value for tPWRGD and use the following equation: C tI VVRAMP PWRGD RAMP INT GS = × −− () .limit 12 Design Information, cont’d. Auto-retry can be approximated as a 555-timer with 2.5 µA charge up and charge down currents through 8V, to a count of 256. Therefore, T= 28 256

2.5 A CAUTORETRY ramp

×× ×µ Due to the 2.5µA max charge current a resistor which draws more than 2.5µA below 8V will disable the autoretry. Try to keep this resistor as big as possible, e.g. 2.5M Ω, for most MOSFETs with max Vt of 4V this will vary the 10 µA Ramp current source by only 4/2.5M Ω=1.6µA. 2.5µA 2.5µA Cramp e.g. 28 256 2.5 A Ion =16.4s×× µ ×

Application Information

Supported External Pass Devices The HV301 and HV311 are designed to support N-Channel MOSFETs and IGBTs. Selection of External Pass Devices Since the current limit is likely to be set just slightly higher than maximum continuous load current in a typical system, the continuous current rating of the device will have to be at least equal to the current limit value. The RDS(ON) of the device is likely to be selected based on allowable voltage drop after the hot swap action has been completed. Thus the continuous power dissipation rating of the device can be determined from the following equation: PR ICONT DS ON LIMIT=× () The peak power rating may be calculated from the following equation: PV IPEAK IN LIMIT=× Given these values an external pass transistor may be selected from the manufacturers data sheet. Selection of Current Sense Resistor The power rating of the sense resistor must be greater than IRload 2 × , where Iload is the normal maximum operating load. Kelvin Connection to Sense Resistor Physical layout of the printed circuit board is critical for correct current sensing. Ideally trace routing between the current sense resistor and the V EE and SENSE pins should be direct and as short as possible with zero current in the sense traces. The use of Kelvin connection from SENSE pin and V EE pin to the respec- tive ends of the current sense resistor is recommended. Paralleling External Pass Transistors Due to variations in threshold voltages and gain characteristics between samples of transistors reliable 50% current sharing is not achievable. Some measure of paralleling may be accom- plished by adding resistors in series with the source of each device; however, it will cause increased voltage drop and power dissipation. Paralleling of external Pass devices is not recommended! If a sufficiently high current rated external pass transistor cannot be found then increased current capability may be achieved by connecting independent hotswap circuits in parallel, since they act as current sources during the load capacitor charging time when the circuits are in current limit. For this application the HV301 with active high PWRGD is recommended where the PWRGD pins of multiple hot swap circuits can be connected in a wired OR configuration. To Negative Terminal of Power Source To Source of MOSFET To VEE Pin Sense Resistor To SENSE Pin

It is critical to have a detailed understanding of the ENABLE input circuitry of the load (DC/DC PWM Converter) in order to make the correct choice between the HV301 or HV311. Many DC/DC PWM Converters reference their ENABLE inputs to the negative input terminal. If the ENABLE input is active LOW then the HV311 can be directly connected as shown below (Application Circuit 1) since the open drain PWRGD output is in a High-Z state until the external MOSFET is fully turned on and the potential on the negative input of the converter is essentially the same as the VEE pin of the HV311. VDD UV OV VEE SENSE GATERAMP -48V 12.5mΩ 487kΩ 6.81kΩ 9.76kΩ IRF530 Cload +5V HV311 COM GND 10nF DC/DC PWM CONVERTER PWRGD ENABLE 574 6 Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV.

However, if the DC/DC PWM Converter with the ENABLE input circuit configuration was active HIGH, then the apparent choice of the HV301 would result in the creation of a current path through the protective diode clamp of the ENABLE input and the PWRGD output MOSFET of the HV301. For this situation the HV311 should be used as shown below in Application Circuit 2. In some applications the PWRGD signal is used to activate load circuitry on the isolated output side of the DC/DC PWM Con- verter. In this situation an optocoupler is needed to provide the required isolation as shown below in Application Circuit 3 . Application Information, cont’d. Application Circuit 2 VDD UV OV VEE SENSE GATERAMP -48V Cload +5V HV311 574 COM GND DC/DC PWM CONVERTER PWRGD ENABLE 12.5mΩ 487kΩ 6.81kΩ 9.76kΩ IRF530 10nF Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV. VDD UV OV VEE SENSE GATERAMP -48V Cload +5V HV311

2 COM

12.5mΩ 487kΩ 6.81kΩ 9.76kΩ IRF530 10nF 574 6 DC/DC PWM CONVERTER PWRGD ENABLE Rload Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV.

When the details of the load ENABLE circuitry is not known, using an optocoupler always provides a safe solution (Application Circuit 4 ). Application Information, cont’d. Application Circuit 5 Filtering Voltage Spikes on Input Supply In some systems over voltage spikes of very short duration may exist. For these systems a small capacitor may be added from the OV pin to the VEE pin to filter the voltage spikes (Application Circuit 5). Application Circuit 4 VDD UV OV VEE SENSE GATERAMP -48V Cload +5V HV311 60mΩ 487kΩ 6.81kΩ 9.76kΩ IRF530 10nF 574 6 DC/DC PWM CONVERTER PWRGD / PWRGD ENABLE / ENABLE Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV. VDD UV OV VEE SENSE GATERAMP -48V 12.5mΩ 487kΩ 6.81kΩ 9.76kΩ IRF530 Cload +5V HV301/ HV311 574 COM GND 10nF PWRGD / PWRGD DC/DC PWM CONVERTER ENABLE / ENABLE Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV.

Application Information, cont’d. Application Circuit 7 Using Short Connector Pin In some systems short connector pins are used to guarantee that the power pins are fully mated before the hotswap control circuit is enabled. For these systems the positive (VDD) end of the R1, R2, and R3 resistor divider should be connected to the short pin (Application Circuit 7 ). Unfortunately this will also cause some delay in responding to UV conditions. If this UV delay is not acceptable, then separate resistor dividers can be provided for OV and UV with a capacitor connected from OV pin to the V EE pin (Application Circuit 6 ). Application Circuit 6 VDD UV OV VEE SENSE GATERAMP -48V 12.5mΩ 475kΩ 16.2kΩ 511kΩ IRF530 Cload +5V HV311 574 COM GND 10nF 10kΩ DC/DC PWM CONVERTER PWRGD / PWRGD ENABLE / ENABLE Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV. VDD UV OV VEE SENSE GATERAMP -48V 12.5mΩ 487kΩ 6.81kΩ 9.76kΩ IRF530 Cload +5V HV301/ HV311 574 COM GND 10nF Long Pin Short Pin Long Pin GND DC/DC PWM CONVERTER PWRGD / PWRGD ENABLE / ENABLE Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV.

If separate resistor dividers are used for OV and UV, then only the positive (V DD) end of the UV resistor divider should be connected to the short pin ( Application Circuit 8 ). If a system requires the use of a short connector pin on the negative supply lead to guarantee that the power pins are fully Application Information, cont’d. Application Circuit 9 Application Circuit 8 mated before the hotswap control circuit is enabled and a single resistor divider string (R1, R2 and R3) is used, then a 6.2V to 10V zener diode must be connected from the UV pin to the V EE pin, as seen below in Application Circuit 9 . VDD UV OV VEE SENSE GATERAMP -48V IRF530 475K 16.2K 511K Cload +5V HV311 574 COM GND 10nF 12.5mΩ 10K Long Pin Long Pin Short Pin GND DC/DC PWM CONVERTER PWRGD / PWRGD ENABLE / ENABLE Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV. VDD UV OV VEE SENSE GATERAMP -48V 12.5mΩ 487kΩ 6.81kΩ 9.76kΩ IRF530 Cload +5V HV311 576 4 COM GND 10nF Long Pin Short Pin Long Pin -48V 6.2V DC/DC PWM CONVERTER PWRGD / PWRGD ENABLE / ENABLE Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV.

Application Information, cont’d. Application Circuit 11 Increasing Under Voltage Hysteresis If the internally fixed under voltage hysteresis is insufficient for a particular system application, then it may be increased by using separate resistor dividers for OV and UV and providing a resistor feedback path from the GATE pin to the UV pin ( Application Circuit 11). If a system requires the use of a short connector pin on the negative supply lead to guarantee that the power pins are fully mated before the hotswap control circuit is enabled and uses separate resistor dividers for UV and OV, then a 6.2V to 10V zener diode must be connected from the OV pin to the V EE pin and only the OV divider should be connected to the short pin (Application Circuit 10 ). Application Circuit 10 VDD UV OV VEE SENSE GATERAMP -48V 12.5mΩ 475kΩ 16.2kΩ 511kΩ IRF530 Cload +5V HV301/ HV311 574 COM GND 10nF 10kΩ-48V 6.2V Long Pin Short Pin Long Pin DC/DC PWM CONVERTER PWRGD / PWRGD ENABLE / ENABLE Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV. VDD UV OV VEE SENSE GATERAMP -48V 12.5mΩ 475kΩ 16.2kΩ 511kΩ IRF530 Cload +5V HV301/ HV311 574 COM GND 10nF 10kΩR6 DC/DC PWM CONVERTER PWRGD / PWRGD ENABLE / ENABLE Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV.

Reverse Polarity Protection The UV and OV pins are protected against reverse polarity input supplies by internal clamping diodes and the fault currents are sufficiently limited by the impedance of the external resistor divider, however, a low current diode with a 100V breakdown rating must be inserted in series with the V DD pin. Application Information, cont’d. This method (shown in Application Circuit 12) will protect the hotswap control circuit however, due to the intrinsic diode in the external MOSFET, the load will not be protected from reverse polarity voltages. Application Circuit 12 VDD UV OV VEE SENSE GATERAMP -48V 12.5mΩ 487kΩ 6.81kΩ 9.76kΩ IRF530 Cload +5V HV311 574 COM GND 10nF DC/DC PWM CONVERTER PWRGD / PWRGD ENABLE / ENABLE Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV.

Many systems use redundant primary power supplies or battery backup. When redundant AC powered sources are used they are generally diode OR’ed to the load on the hot terminal. For these systems, the use of independent hotswap controllers is recommended with the diode OR’ing provided after the hotswap Application Information, cont’d. controllers. The HV311 is ideally suited for such applications since two or more active low PWRGD signals can be connected to a single active low ENABLE pin, thus enabling the load as long as at least one primary power source is available. By adding low current 100V diodes in series with the V DD pins, full reverse polarity protection on either power source is also provided (Application Circuit 13 ). Application Circuit 13 VDD UV OV VEE SENSE GATERAMP -48V Cload +5V -48V 60mΩ 487kΩ 6.81kΩ 9.76kΩ IRF530 574 GND 10nF PS1 PS2 HV301/ HV311 HV301/ HV311 PWRGD PWRGD 487kΩ 6.81kΩ 9.76kΩ 574 6 60mΩ IRF530 10nF DC/DC PWM CONVERTER ENABLE / ENABLE Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV.

Application Information, cont’d. Use with Negative Ground Either the HV301 or HV311 may be used with any negative ground systems where DC/DC PWM Converters have isolated outputs and their inputs need not be ground referenced (Application Circuit 14 ). Application Circuit 14 Current Limit Stability (Method 2 (Servo) Only) The closed loop current mode control system used in the HV301/ HV311 is very stable, especially when driving MOSFETs with high gate capacitances (CISS). However, a peaking in ILIMIT near the end of the current limit may be noted with some MOSFETs. The current control loop can be frequency compensated to eliminate this peaking by adding a series connected capacitor and resistor between the gate and source of the external MOSFET. The recommended starting values for C and R are 10nF and 1K. These compensation values should be verified by board level testing, which may yield satisfactory results with reduced com- ponent values. VDD UV OV VEE SENSE GATERAMP +48V Cload +5V HV301/ HV311 12.5mΩ 487kΩ 6.81kΩ 9.76kΩ IRF530 10nF DC/DC PWM CONVERTER PWRGD / PWRGD ENABLE/ ENABLE 574 6 Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV.

Application Information cont’d. Extending Circuit Breaker Delay Connecting a resistor in series with the SENSE pin and a capacitor between the SENSE and V EE pins as shown in the following diagram may be used to extend the Circuit Breaker delay time beyond the 5µs internally set delay time (Application Circuit 15). The time delay achievable by this method is limited since this Application Circuit 15 delay circuit will also effect the current control feedback loop and will result in a current overshoot during the external pass device turn on transition to current limit. If the time delay required for the Circuit Breaker causes excessive current overshoot during the turn on transition then the following circuit may be used, where the RC filter is switched on after the completion of the current limit control function of the hotswap controller. VDD UV OV VEE SENSE GATERAMP -48V Cload +5V HV301/ HV311 12.5mΩ 487kΩ 6.81kΩ 9.76kΩ IRF530 574 6 Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV.

Application Information cont’d. Latched Operation For those applications that need to disable the automatic retry capability, the following circuit disables the auto retry feature. Application Circuit 17 VDD UV OV VEE SENSE GATE RAMP -48V Cload +5V HV301 / HV311 487kΩ 6.81kΩ 9.76kΩ 12.5mΩ IRF530 2.5MΩ Note: capacitor may be needed to slow PWRGD dv/dt if oscillations are observed when V IN is close to OV.

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com 08/26/02 rev.11b ©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. Package Dimensions 0° – 8° 45° 7° (4 PLCS) 0.193 ± 0.012 (4.90 ± 0.30) D 0.192 ± 0.005 (4.89 ± 0.11) 0.154 ± 0.004 (3.91 ± 0.10) E0.236 ± 0.008 (5.99 ± 0.20) H 0.061 ± 0.008 (1.55 ± 0.20) A 0.007 ± 0.003 (0.178 ± 0.076) TYP .0.050 (1.20) e 0.016 ± 0.002 (0.406 ± 0.05) B C0.010 ± 0.002 (0.254 ± 0.051) 0.035 ± 0.015 (0.889 ± 0.381) L h 0.020 ± 0.009 (0.508 ± 0.229) 0.0275 ± 0.0025 (0.698 ± 0.064) Circled letters (e.g. denote JEDEC reference dimensons.B Inches (Millimeters)