HV2801

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Document overview

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Technical content

Features

► 32-Channel high voltage analog switch ► 2:1 Multiplexer / Demultiplexer ► 3.3V or 5.0V CMOS input logic level ► 20MHz data shift clock frequency ► HVCMOS technology for high performance ► Very low quiescent power dissipation -10µA ► Low parasitic capacitance ► DC to 50MHz analog signal frequency ► -60dB typical OFF-isolation at 5.0MHz ► CMOS logic circuitry for low power ► Excellent noise immunity ► Cascadable serial data register with latches ► Flexible operating supply voltages

Applications

► Medical ultrasound imaging ► NDT metal flaw detection ► Piezoelectric transducer drivers ► Inkjet printer heads ► Optical MEMS modules General Description The Supertex HV2801 is a low charge injection 32-channel high voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer driver, and printers. Input data are shifted into a 32-bit shift register that can then be retained in a 32-bit latch. To reduce any possible clock feed through noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., V PP/VNN: +40V/-160V, +100V/-100V, and +160V/-40V. Block Diagram Low Charge Injection 32-Channel High Voltage Analog Switch Level Shifters VPPVNN Latches CLRLE 32-Bit Shift Register CLK DIN GNDVDD Output Switches DOUT SW0 SW1 Y01 SW2 SW3 Y23 SW28 SW29 Y2829 SW30 SW31 Y3031 D LE CLR D LE CLR D LE CLR D LE CLR D LE CLR D LE CLR D LE CLR D LE CLR

Supertex inc. www.supertex.com Doc.# DSFP-HV2801 NR013113 Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Parameter Value VDD logic supply -0.5V to +6.5V VPP-VNN differential supply 220V VPP positive supply -0.5V to VNN +200V VNN negative supply +0.5V to -200V Logic input voltage -0.5V to VDD +0.3V Analog signal range VNN to VPP Peak analog signal current/channel 3.0A Storage temperature -65°C to 150°C Power dissipation 1.5W Recommended Operating Conditions Sym Parameter Value VDD Logic power supply voltage 3.0V to 5.5V VPP Positive high voltage supply +40V to VNN +200V VNN Negative high voltage supply -40V to -160V VIH High level input voltage 0.9VDD to VDD VIL Low level input voltage 0V to 0.1VDD VSIG Analog signal voltage peak-to-peak VNN +10V to VPP -10V TA Operating free air temperature 0OC to 70OC Pin Configuration Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. Product Marking 64-Lead QFN (K6) 64-Lead QFN (K6) (top view) Package may or may not include the following marks: Si or L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = “Green” Packaging HV2801K6 LLLLLLLLL YYWW AAA CCC -G indicates package is RoHS compliant (‘Green’)

Ordering Information

Part Number Package Option Packing HV2801K6-G 64-Lead QFN (9x9) 260/Tray Typical Thermal Resistance Package θja 64-Lead QFN 21OC/W

Supertex inc. www.supertex.com Doc.# DSFP-HV2801 NR013113 Sym Parameter 0OC +25OC +70OC Unit Conditions Min Max Min Typ Max Min Max RONS Small signal switch ON-resistance - 30 - 26 38 - 48 Ω I SIG = 5.0mA VPP = +40V, VNN = -160V- 25 - 22 27 - 32 ISIG = 200mA - 25 - 22 27 - 30 ISIG = 5.0mA VPP = +100V, VNN = -100V- 18 - 18 24 - 27 ISIG = 200mA - 23 - 20 25 - 30 ISIG = 5.0mA VPP = +160V, VNN = -40V- 22 - 16 25 - 27 ISIG = 200mA ΔRONS Small signal switch ON-resistance matching - 20 - 5.0 20 - 20 % I SIG = 5.0mA, VPP = +100V, VNN = -100V RONL Large signal switch ON-resistance - - - 15 - - - Ω V SIG = VPP -10V, ISIG = 1A ISOL Switch OFF-leakage per switch - 5.0 - 1.0 10 - 15 μA VSIG = VPP -10V, VNN +10V VOS DC offset switch OFF - 300 - 100 300 - 300 mV 100kΩ loadDC offset switch ON - 500 - 100 500 - 500 IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches OFFINNQ Quiescent VNN supply current - - - -10 -50 - - IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches ON, I SW = 5.0mAINNQ Quiescent VNN supply current - - - -10 -50 - - fSW Output switching frequency - - - - 50 - - kHz Duty cycle = 50% IPP Average VPP supply current - 16 - - 20 - 22 mA VPP= +40V, VNN = -160V All output switches are turning ON and OFF at 50kHz with no load - 14 - - 14 - 14 V PP= +100V, VNN = -100V - 14 - - 14 - 14 VPP= +160V, VNN = -40V INN Average VNN supply current - 16 - - 20 - 22 mA VPP = +40V, VNN = -160V All output switches are turning ON and OFF at 50kHz with no load - 14 - - 14 - 14 V PP= +100V, VNN = -100V - 14 - - 14 - 14 VPP= +160V, VNN = -40V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 μA All logic inputs are static CIN Logic input capacitance - 10 - - 10 - 10 pF --- * See Test Circuits on page 5

Supertex inc. www.supertex.com Doc.# DSFP-HV2801 NR013113 Sym Parameter 0OC +25OC +70OC Unit ConditionsMin Max Min Typ Max Min Max tSD Set up time before LE rises 25 - 25 - - 25 - ns --- tWLE Time width of LE 56 - - 56 - 56 - ns VDD = 3.0V 12 - - 12 - 12 - VDD = 5.0V tDO Clock delay time to data out 8.0 40 8.0 19 40 8.0 40 ns VDD = 3.0V 8.0 30 8.0 15 30 8.0 30 VDD = 5.0V tWCLR Time width of CLR 55 - 55 - - 55 - ns --- tSU Set up time data to clock 21 - 21 - - 21 - ns VDD = 3.0V tH Hold time data from clock ns VDD = 3.0V fCLK Clock frequency - 8 - - 8 - 8 MHz VDD = 3.0V - 20 - - 20 - 20 VDD = 5.0V tR, tF Clock rise and fall times - 50 - - 50 - 50 ns --- tON Turn ON time - 5.0 - - 5.0 - 5.0 μs VSIG = VPP -10V, RLOAD = 10kΩtOFF Turn OFF time - 5.0 - - 5.0 - 5.0 dv/dt Maximum VSIG slew rate - 20 - - 20 - 20 V/ns VPP = +40V, VNN = -160V - 20 - - 20 - 20 VPP = +100V, VNN = -100V - 20 - - 20 - 20 VPP = +160V, VNN = -40V KO OFF isolation dB f = 5.0MHz, 1.0kΩ//15pF load -58 - -58 -60 - -58 - f = 5.0MHz, 50Ω load K CR Switch crosstalk -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load IID Output switch isolation diode current - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle C SG(OFF) OFF capacitance SW to GND - 14 - 9.0 14 - 14 pF VSIG = 0, f = 1.0MHz, both SW OFFOFF capacitance Y to GND - 28 - 18 28 - 28 CSG(ON) ON capacitance SW to GND - 33 - 23 33 - 33 pF VSIG = 0, f = 1.0MHz, one SW ON, one SW OFFON capacitance Y to GND - 33 - 23 33 - 33 +VSPK Output voltage spike SW - - - - +150 - - mV VPP = +40V, VNN = -160V RLOAD = 50Ω-VSPK - - - - -150 - - +VSPK - - - - +150 - - VPP = +100V, VNN = -100V RLOAD = 50Ω-VSPK - - - - -150 - - +VSPK - - - - +150 - - VPP = +160V, VNN = -40V RLOAD = 50Ω-VSPK - - - - -150 - - * See Test Circuits on page 5

Supertex inc. www.supertex.com Doc.# DSFP-HV2801 NR013113 Sym Parameter 0OC +25OC +70OC Unit ConditionsMin Max Min Typ Max Min Max +VSPK Output voltage spike Y - - - - +150 - - mV VPP = +40V, VNN = -160V RLOAD = 50Ω-VSPK - - - - -150 - - +VSPK - - - - +150 - - VPP = +100V, VNN = -100V RLOAD = 50Ω-VSPK - - - - -150 - - +VSPK - - - - +150 - - VPP = +160V, VNN = -40V RLOAD = 50Ω-VSPK - - - - -150 - - QC Charge injection - - - 820 - - - pC VPP = +40V, VNN = -160V

Supertex inc. www.supertex.com Doc.# DSFP-HV2801 NR013113 Test Circuits SW1SW0 Y01 SW1SW0 Y01 SW1 SW0 Y01 SW1SW0 Y01 SW1SW0 Y01 SW1 SW0 Y01 SW1SW0 Y01 SW1SW0 Y01 VPP -10V Switch OFF Leakage DC Offset ON/OFF TON/TOFF Test Circuit OFF Isolation Isolation Diode Current Charge Injection Output Voltage Spike SW VPP VPP VDD 5.0V VNN VNN GND VPP VPP VDD 5.0V VNN VNN GND VPP VPP VDD 5.0V VNN VNN GND VPP VPP VDD 5.0V VNN VNN GND VPP VPP VDD 5.0V VNN VNN GND VPP VPP VDD 5.0V VNN VNN GND VPP VPP VDD 5.0V VNN VNN GND Output Voltage Spike Y KO = 20Log VOUT VIN VIN = 10VP-P @5.0MHz RLOAD 10kΩ VOUT VOUT VOUT VOUT VOUT VOUT ΔVOUT NC NC NC NC NC NC VPP -10V ISOL VSIG IID VNN NC NC NC Q = 1000pF • ∆VOUT 50Ω 50Ω RL 1kΩ NC 1000pF +VSPK -VSPK +VSPK -VSPK RL 1kΩ 50Ω RLOAD 100kΩ 50Ω Crosstalk KCR = 20Log VOUT VIN Y01 50Ω NC Y23 SW1 SW3 SW2 SW0 VPP VPP VDD 5.0V VNN VNN GND VIN = 10VP-P @5.0MHz VPP VPP VDD 5.0V VNN VNN GND NC VOUT

Supertex inc. www.supertex.com Doc.# DSFP-HV2801 NR013113 Logic Timing Waveforms Truth Table DATA IN LE CLOCK OFF ON VOUT (typ) 50% 50% 50% 50% tWLE tSD 50% 50% tSU th tOFF 50% tDO tON tWCL CLR DN+1 DN DN-1 50% 50% 90% 10% DATA OUT L - ... - - ... - L L OFF - ... - - ... X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF Notes: 1. The 32 switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. All 32 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch. 4. D OUT is high when data in the register 31 is high. 5. Shift registers clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs.

Supertex inc. www.supertex.com Doc.# DSFP-HV2801 NR013113 Pin Function

1 SW30

2 Y3031

3 SW31

5 CLR

8 CLK

9 VDD

10 DIN

11 GND

12 DOUT

14 SW0

15 Y01

16 SW1

17 SW2

18 Y23

19 SW3

20 SW4

21 Y45

22 SW5

23 SW6

24 Y67

25 SW7

26 SW8

27 Y89

28 SW9

29 SW10

30 Y1011

31 SW11

32 SW12

33 Y1213

34 SW13

35 VPP

37 VNN

38 SW14

39 Y1415

40 SW15

41 SW16

42 Y1617

43 SW17

44 VNN

46 VPP

47 SW18

48 Y1819

49 SW19

50 SW20

51 Y2021

52 SW21

53 SW22

54 Y2223

55 SW23

56 SW24

57 Y2425

58 SW25

59 SW26

60 Y2627

61 SW27

62 SW28

63 Y2829

64 SW29

VSUB (Thermal Pad) The central thermal pad on the bottom of package must be connected to VNN externally

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com HV2801 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV2801 NR013113 64-Lead QFN Package Outline (K6) 9.00x9.00mm body, 1.00mm height (max), 0.50mm pitch Seating Plane Top View Side View Bottom View D E View B View B Note 3 Note 2 Note 1 (Index Area D/2 x E/2) Note 1 (Index Area D/2 x E/2) e b L A θ Symbol A A1 A3 b D D2 E E2 e L L1 θ Dimension (mm) MIN 0.80 0.00 0.20 REF 0.50 BSC 0.30 0.00 0O Drawings are not to scale. Supertex Doc.#: DSPD-64QFNK69X9P050, Version B020112 Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square.