HV2731

HV2731 SUTEX | Alldatasheet

Document overview

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Technical content

Features

HVCMOS® technology for high performance 220V operating conditions 22Ω typical output on-resistance Integrated bleed resistors on the outputs 3.3V and 5.0V CMOS logic compatibility Very low quiescent power dissipation (-10µA) -45dB min off isolation at 7.5MHz Low parasitic capacitance Excellent noise immunity Flexible operating supply voltages 48-lead LQFP package

Applications

Medical ultrasound imaging Non-destructive evaluation General Description The Supertex HV2731 is a 220V, 16-channel, high voltage, analog switch integrated circuit (IC) with output bleed resistors (R INT). The output switches are confi gured as 2 sets of 8 single pole, single throw analog switches. The IC is intended to be used in applications requiring high voltage switching controlled by low voltage control signals, such as ultrasound imaging. The 2 sets of 8 analog switches are controlled by 2 input logic controls, D IN1 and DIN2. A logic high on DIN1 will turn on switches 0 to 7 and a logic high on D IN2 will turn on switches 8 to 15. The bleed resistors help to signifi cantly reduce voltage built up on capacitive loads such as piezoelectric transducers connected to the outputs. Using HVCMOS ® technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide effi cient control of high voltage analog signals. Block Diagram 16-Channel (2 Banks of 8-Channels), High Voltage, Analog Switch With Bleed Resistors LE VPP VNN VDD DIN1 SW0 GND VDD SW0 SW7 SW7 SW8 SW8 SW15 SW15 DIN2 RGND Level Translator 2 Latch Latch Level Translator 1

-G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Parameter Value VDD logic supply -0.5V to +7.0V VPP-VNN differential supply 225V VPP positive supply -0.5V to V NN+225V VNN negative supply +0.5V to -225V Logic input voltage -0.5V to V DD +0.3V Analog signal range V NN to VPP Peak analog signal current/channel 3.0A Storage temperature -65°C to 150°C Power dissipation 1.0W Recommended Operating Conditions Sym Parameter Value VDD Logic power supply voltage 3.0V to 5.5V VPP Positive driver supply +50V to +110V VNN Negative high voltage supply -10V to V PP -220V VIH High level input voltage V DD -1.0V to VDD VIL Low-level input voltage 0V to 1.0V VSIG Analog signal voltage peak-to-peak V NN +10V to VPP -10V TA Operating free air temperature 0 OC to 70OC Product Marking YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV2731FG LLLLLLLLL CCCCCCCC AAA 48-Lead LQFP (FG) Pin Confi guration Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up fi rst and powered-down last. 2. V SIG must be VNN ≤ VSIG ≤ VPP or fl oating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec.

Ordering Information

7x7mm body, 1.4mm height (min), 0.50mm pitch HV2731 HV2731FG-G 48-Lead LQFP (FG) (top view)

(Over recommended operating conditions unless otherwise specifi ed ) Sym Parameter 0OC+ 2 5 OC+ 7 0 OC Units Conditions Min Max Min Typ Max Min Max RONS Small signal switch on-resistance - 30 - 26 32 - 40 Ω VSIG = 0V, ISIG = 5.0mA, VPP = +50V, VNN = -170V - 25 - 22 27 - 35 VSIG = 0V, ISIG = 200mA, VPP = +50V, VNN = -170V - 15 - 22 27 - 30 VSIG = 0V, ISIG = 5.0mA, VPP = +110V, VNN = -110V - 20 - 18 22 - 25 VSIG = 0V, ISIG = 200mA, VPP = +110V, VNN = -110V ΔRONS Small signal switch on-resistance matching - 20 - 5.0 20 - 20 % VSIG = 0V, ISIG = 5.0mA, VPP = +110V, VNN = -110V RONL Large signal switch on-resistance --- 1 5 --- Ω V SIG = 0V, ISIG = 1.0A RINT Output switch shunt resis- tance - - 20 35 50 - - KΩ Output switch to RGND IRINT = 0.5mA ISOL Switch off-leakage per switch - 5.0 - 1.0 10 - 15 μA V SIG = VPP -10V, VNN = +10V VOS(OFF) DC offset switch off - 300 - 100 300 - 300 mV No load VOS(ON) DC offset switch on - 500 - 100 500 - 500 IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches off INNQ Quiescent VNN supply current - - - -10 -50 - - IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches on, ISW = 5.0mAINNQ Quiescent VNN supply current - - - -10 -50 - - fSW Output switching frequency - - - - 50 - - kHz Duty cycle = 50% IPP Average VPP supply current - 8.1 - - 8.8 - 10 mA VPP = 50V, VNN = -170V, All switches turning on and off at 50kHzI NN Average VNN supply current - -8.1 - - -8.8 - -10 IPP Average VPP supply current - 8.1 - - 6.3 - 6.9 mA VPP = 110V, VNN = -110V, All switches turning on and off at 50kHzI NN Average VNN supply current - -8.1 - - -6.3 - -6.9 IDDQ Quiescent VDD supply current - 10 - - 10 - 10 μA All logic inputs are static IDD Average VDD supply current - 2.0 - - 2.0 - 2.0 mA DIN1 = DIN2 = 3.0MHz, LE = high CIN Logic input capacitance - 10 - - 10 - 10 pF --- Sym Parameter 0OC+ 2 5 OC+ 7 0 OC Units Conditions Min Max Min Typ Max Min Max tWLE Time width of LE 150 - 150 - - 150 - ns --- tWDIN Time width of DIN 150 - 150 - - 150 - ns --- tSD Set up time before LE rises 150 - 150 - - 150 - ns ---

(Over recommended operating conditions unless otherwise specifi ed) Sym Parameter 0OC+ 2 5 OC+ 7 0 OC Units Conditions Min Max Min Typ Max Min Max tON Turn on time - 5.0 - - 5.0 - 5.0 μs VSIG = VPP -10V, RLOAD = 10KΩtOFF Turn off time - 5.0 - - 5.0 - 5.0 dv/dt Maximum V SIG slew rate - 20 - - 20 - 20 V/ns --- KO Off isolation -30 - -30 -33 - -30 - dB f = 5.0MHz, load = 1.0KΩ/15pF -45 - -45 -50 - -45 - f = 7.5MHz, R LOAD = 50KΩ KCR Switch crosstalk -45 - -45 - - -45 - dB f = 5.0MHz, R LOAD = 50KΩ IID Output switch isolation diode current - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle CSG(OFF) Off capacitance SW to GND 5.0 17 5.0 12 17 5.0 17 pF V SIG = 0V, f = 1.0MHz CSG(ON) On capacitance SW to GND 25 50 25 38 50 25 50 pF V SIG = 0V, f = 1.0MHz +VSPK Output voltage spike --- 2 5 0 --- mV R LOAD = 50Ω QC Charge injection --- 7 7 0 --- PC VPP = +50V, VNN = -170V Logic Timing Waveforms VDD DIN tsd tWLE LE SW ON OFF 10% 90% 50% VDD TON TOFF 50% 50% 50% Truth Table DIN2 DIN1 LE SW0 to SW7 SW8 to SW15 L L L OFF OFF L H L ON OFF H L L OFF ON HHL O N O N X X H Hold Previous State

5.0V DC Offset ON/OFF RGND VOUT VPP VNN VDD GND 5.0V TON/TOFF RGND VOUT VPP VNN VPP VNN RINTRINT RINTRINT VPP-10V RL 10KΩ VPP VNN VDD GND 5.0V Switch OFF Leakage RGND VPP-10V and VNN+10V VPP VNN RINTRINT VOUT VOUTISOL RINT VPP VNN VDD GND 5.0V Off Isolation RGND VPP VNN RINTRINT VOUT VOUT VIN KO = 20Log RLOAD VIN=10VP-P @ 5.0MHz VPP VNN VDD GND 5.0V Crosstalk RGND VPP VNN RINTRINT VOUT VOUT VIN KCR = 20Log VIN=10VP-P @ 5.0MHz 50Ω NC 50Ω VPP VNN VDD GND 5.0V Isolation Diode Current RGND VSIG VPP VNN RINT RINT VNN IID VPP VNN VDD GND 5.0V Output Voltage Spike RGND VPP VNN RINTRINT VOUT 1KΩ 50Ω +VSPK -VSPK VPP VNN VDD GND 5.0V Charge Injection RGND VPP VNN RINTRINT VOUT Q = 1000pF x ∆VOUT VSIG 1000pF ∆VOUT

1 VNN 25 SW10

2 N/C 26 SW10

3 VPP 27 SW9

4 N/C 28 SW9

8 N/C 32 SW7

9 N/C 33 SW6

10 VDD 34 SW6

11 GND 35 SW5

12 N/C 36 SW5

13 RGND 37 SW4

14 SW15 38 N/C

15 SW15 39 SW4

16 SW14 40 N/C

17 SW14 41 SW3

18 SW13 42 SW3

19 SW13 43 SW2

20 SW12 44 SW2

21 SW12 45 SW1

22 SW11 46 SW1

23 SW11 47 SW0

24 N/C 48 SW0

Pin Confi guration

(The package drawing (s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV2731 NR020508 48-Lead LQFP Package Outline (FG) 7x7mm body, 1.4mm height (min), 0.50mm pitch Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ Dimension (mm) 0.50 BSC 0.45 1.00 REF 0.25 BSC JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. Drawings not to scale.

1 Seating

θL View B View B Seating Plane Top View D E b e Side View A2A Note 1 (Index Area D1/4 x E1/4) Note 1: A Pin 1 identifi er must be located in the index area indicated. The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature.