HV2701

HV2701_07 SUTEX | Alldatasheet

Document overview

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Technical content

Features

HVCMOS technology for high performance Integrated bleed resistors on the outputs

16 Channels of high voltage analog switch

3.3V input logic level compatible 20MHz data shift clock frequency Very low quiescent power dissipation-10µA Low parasitic capacitance DC to 10MHz analog signal frequency -60dB typical off-isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity Cascadable serial data register with latches Flexible operating supply voltages

Applications

Medical ultrasound imaging NDT metal fl aw detection Piezoelectric transducer drivers Optical MEMS modules General Description The Supertex HV2701 is a low charge injection, 16-channel, high voltage, analog switch integrated circuit (IC) with bleed resistors. The device can be used in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging and piezoelectric transducer drivers. The bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. Input data is shifted into a 16-bit shift register that can then be retained in a 16-bit latch. To reduce any possible clock feed-through noise, the latch enable bar should be left high until all bits are clocked in. Data is clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide effi cient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., V PP/VNN: +40V/-160V, +100V/-100V, and +160V/-40V. Block Diagram Low Charge Injection 16-Channel High Voltage Analog Switch with Bleed Resistors D LE CL D LE CL D LE CL D LE CL D LE CL Latches Level Shifters Output Switches SW0 SW1 SW2 SW14 SW15 16-Bit Shift Register RGNDVPPVNNCLLEVDD GND DOUT CLK DIN

Ordering Information

48-Lead LQFP (FG) (7x7x1.4mm body, 0.50mm pitch) HV2701 HV2701FG-G Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Recommended Operation Conditions Symbol Parameter Value VDD Logic power supply voltage 3.0V to 5.5V VPP Positive high voltage supply +40V to V NN +200V VNN Negative high voltage supply -40V to –160V VIH High level input voltage 0.9V DD to VDD VIL Low level input voltage 0V to 0.1V DD VSIG Analog signal voltage peak-to- peak VNN+10V to VPP- 0V TA Operating free air temperature 0°C to 70°C Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up fi rst and powered- down last. 2. V SIG must be within VNN and VPP or fl oating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. Parameter Value VDD Logic supply -0.5V to +7V VPP-VNN differential supply 220V VPP Positive supply -0.5V to V NN+200V VNN Negative supply +0.5V to -200V Logic input voltage -0.5V to V DD +0.3V Analog signal range V NN to VPP Peak analog signal current/channel 3.0A Storage temperature -65°C to 150°C Power dissipation 1.0W Product Marking 48-Lead LQFP Package (FG) -G indicates package is RoHS compliant (‘Green’) YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV2701FG LLLLLLLLL CCCCCCCC AAA Pin Confi guration 48-Lead LQFP Package (FG) (top view)

0°C +25°C +70°C Units Conditions Min Max Min Typ Max Min Max RONS Small signal switch on-resistance - 30 - 26 38 - 48 Ω ISIG = 5.0mA VPP = +40V VNN = -160V-2 5-2 2 2 7- 3 2 I SIG = 200mA -2 5-2 2 2 7- 3 0 I SIG = 5.0mA VPP = +100V VNN = -100V- 18 - 18 24 - 27 I SIG = 200mA - 23 - 20 25 - 30 I SIG = 5.0mA VPP = +160V VNN = -40V- 22 - 16 25 - 27 I SIG = 200mA ∆RONS Small signal switch on-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5.0mA, VPP = +100V, VNN = -100V RONL Large signal switch on-resistance --- 1 5 -- - Ω V SIG= VPP -10V, ISIG = 1.0A RINT Value of output bleed resistor - - 20 35 50 - - KΩ Output Switch to RGND IRINT = 0.5mA ISOL Switch off leakage per switch* - 5.0 - 1.0 10 - 15 µA V SIG = VPP -10V and VNN +10V VOS DC offset switch off* - 300 - 100 300 - 300 mV No Load DC offset switch on* - 500 - 100 500 - 500 mV IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches off INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches off IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches on, I SW = 5.0mA INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches on, I SW = 5.0mA fSW Output switching frequency ---- 5 0 - -k H z Duty cycle = 50% IPP Average VPP supply current mA VPP = +40V VNN = -160V All output switches are turning On and Off at 50KHz with no load. V PP = +100V VPP = +160V INN Average VNN supply current mA VPP = +40V VNN = -160V VPP = +100V VPP = +160V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 µA All logic inputs are static CIN Logic input capacitance - 10 - - 10 - 10 pF --- (over recommended operating conditions unless otherwise noted) * See Test Circuits on page 5

(over recommended operating conditions, VDD= 5.0V, tR = tF ≤ 5.0ns, 50% duty cycle, CLOAD = 20pF, unless otherwise noted) Sym Parameter 0°C +25°C +70°C Units ConditionsMin Max Min Typ Max Min Max tSD Set up time before LE rises 25 - 25 - - 25 - ns --- tWLE Time width of LE 56 - - 56 - 56 - ns VDD = 3.0V 12 - - 12 - 12 - V DD = 5.0V tDO Clock delay time to data out 50 100 50 78 100 50 100 ns VDD = 3.0V 15 40 15 30 40 15 40 V DD= 5.0V tWCL Time width of CL 55 - 55 - - 55 - ns --- tSU Set up time data to clock 21 - - 21 - 21 - ns VDD= 3.0V 7--7-7- V DD= 5.0V tH Hold time data from clock 2 - 2 - - 2 - ns V DD= 3.0 or 5.0V fCLK Clock frequency -8--8-8 MHz VDD= 3.0V -2 0- -2 0-2 0 V DD= 5.0V tR,tF Clock rise and fall times - 50 - - 50 - 50 ns ---- TON Turn ON time* - 5.0 - - 5.0 - 5.0 µs V SIG = VPP-10V, RLOAD = 10KΩ TOFF Turn OFF time* - 5.0 - - 5.0 - 5.0 µs V SIG = VPP-10V, RLOAD = 10KΩ dv/dt Maximum V SIG slew rate -2 0- -2 0-2 0 v/ns VPP = +40V, VNN = -160V -2 0- -2 0-2 0 V PP = +100V, VNN = -100V -2 0- -2 0-2 0 V PP = +160V, VNN = -40V KO Off isolation* dB f = 5.0MHz, 1KΩ//15pF load -58 - -58 - - -58 - f = 5.0MHz, 50Ω load KCR Switch crosstalk* -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load IID Output switch isolation diode current - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle CSG(OFF) Off capacitance SW to GND 5.0 17 5.0 12 17 5.0 17 pF 0V, f = 1.0MHz CSG(ON) On capacitance SW to GND 25 50 25 38 50 25 50 pF 0V, f = 1.0MHz +VSPK Output voltage spike* ---- 1 5 0 -- mV VPP = +40V, VNN = -160V, RLOAD = 50Ω-VSPK +VSPK RLOAD = 50Ω-VSPK +VSPK RLOAD = 50Ω-VSPK QC Charge injection* --- 8 2 0 --- pC VPP= +40V, VNN= -160V, VSIG= 0V VSIG= 0V VSIG= 0V * See Test Circuits on page 5

TURN (TON/TOFF) ON/OFF TIME OFF Isolation Output Switch Isolation Diode Current Switch Crosstalk Q = 1000pF x ΔVOUT Charge Injection Output Voltage Spike RGND RGND RGND RGND RGND RGND RGND RGNDOpen

Notes: 1. The 16 switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data fl ow through the latch. 4. D OUT is high when data in the shift register 15 is high. 5. Shift registers clocking has no effect on the switch states if LE is high. 6. The CL clear input overrides all other inputs. Logic Timing Waveforms DATA IN LE CLOCK DATA OU T OFF ON OUT (TYP) V 50% 50% 50%50% t WLE t SD t SU t h 50%50% t OFF 50% t DO t ON t WC L CLR D N+1 D N D N-1 50%50% 90% 10% ... ... - L L OFF - ... ... -L -- -LL- O F F -- - -- -- -L L-- -- - -- -- -L L-- -- - -- L- -LL-- O F F - - -- -L -LL-- - O F F - -- -- -L L-- -- - -- -- -L L-- -- - -- -- -L L-- -- - -- -- -L L-- -- - -- -- L L L-- -- O F F -- -- H L L-- -- O N X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF

Pin # Function 1N C 2N C 3S W 4 B 4S W 4 A 5S W 3 B 6S W 3 A 7S W 2 B 8S W 2 A 9S W 1 B

10 SW1A

11 SW0B

12 SW0A

Pin # Function

13 VNN

15 VPP

17 GND

18 VDD

19 DIN

20 CLK

22 CLR

23 DOUT

24 RGND

Pin # Function

25 SW15B

26 SW15A

27 SW14B

28 SW14A

29 SW13B

30 SW13A

31 SW12B

32 SW12A

33 SW11B

34 SW11A

Pin # Function

37 SW10B

38 SW10A

39 SW9B

40 SW9A

41 SW8B

42 SW8A

43 SW7B

44 SW7A

45 SW6B

46 SW6A

47 SW5B

48 SW5A

NC = No Internal Connection Pin Confi guration 48-Lead LQFP (FG)

(The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV2701 B060707 48-Lead LQFP Package Outline (FG) 7x7mm body, 1.4mm height (min), 0.50mm pitch Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ Dimension (mm) 0.50 BSC 0.45 1.00 REF 0.25 BSC JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. Drawings not to scale.

1 Seating

θL View B View B Seating Plane Top View D E b e Side View A2A Note 1 (Index Area D1/4 x E1/4) Note 1: A Pin 1 identifi er must be located in the index area indicated. The Pin 1 identifi er may be either a mold, or an embedded metal or marked feature.