HV2661

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Document overview

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Technical content

Features

► 24-channel high voltage analog switch ► 3.3 or 5.0V CMOS input logic level ► 3:1 MUX-deMUX with 8 states ► 20MHz data shift clock frequency ► HVCMOS technology for high performance ► Very low quiescent power dissipation, 10µA ► Low parasitic capacitance ► DC to 50MHz analog signal frequency ► -60dB typical OFF-isolation at 5.0MHz ► CMOS logic circuitry for low power ► Excellent noise immunity ► Cascadable serial data register with latches ► Flexible operating supply voltages

Applications

► Medical ultrasound imaging ► Piezoelectric transducer drivers ► Inkjet printer heads ► Optical MEMS modules General Description The Supertex HV2661 is a low charge injection 24-channel high voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer driver, and printers. Input data is shifted into a 24-bit shift register that can then be retained in a 24-bit latch. To reduce any possible clock feed through noise, the latch enable (LE) should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., V PP/VNN: +40V/-160V, +100V/-100V, and +160V/-40V. Block Diagram Low Charge Injection 24-Channel High Voltage Analog Switch SW0 Level Shifters VPPVNN Latches CLRLE D LE CLR 24-Bit Shift Register CLK DIN DOUT GNDVDD Output Switches SW1 SW2 SW21 SW22 SW23 SW3 SW4 SW5 D LE CLR D LE CLRD LE CLR D LE CLR D LE CLR D LE CLR D LE CLR D LE CLR

Supertex inc. www.supertex.com Doc.# DSFP-HV2661 NR010913 -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Parameter Value VDD logic supply -0.5V to +6.5V VPP-VNN differential supply 220V VPP positive supply -0.5V to VNN+ 200V VNN negative supply +0.5V to - 200V Logic input voltage -0.5V to VDD + 0.3V Analog signal range VNN to VPP Peak analog signal current/channel 3.0A Storage temperature -65°C to 150°C Power dissipation 1.0W Recommended Operating Conditions Sym Parameter Value VDD Logic power supply voltage 3.0V to 5.5V VPP Positive high voltage supply +40V to VNN + 200V VNN Negative high voltage supply -40V to -160V VIH High level input voltage 0.9VDD to VDD VIL Low level input voltage 0V to 0.1VDD VSIG Analog signal voltage peak-to-peak VNN +10V to VPP - 10V TA Operating free air temperature 0OC to 70OC Pin Configuration Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. Product Marking YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV2661FG LLLLLLLLL CCCCCCCC AAA 48-Lead LQFP 48-Lead LQFP (top view) Package may or may not include the following marks: Si or Typical Thermal Resistance Package θja 48-Lead LQFP 52OC/W

Ordering Information

Part Number Package Packing HV2661FG-G 48-Lead LQFP 250/Tray HV2661FG-G M931 48-Lead LQFP 1000/Reel

Supertex inc. www.supertex.com Doc.# DSFP-HV2661 NR010913 Sym Parameter 0OC +25OC +70OC Unit Conditions Min Max Min Typ Max Min Max RONS Small signal switch ON-resistance - - - 26 - - - Ω I SIG = 5.0mA VPP = +40V, VNN = -160V- - - 22 - - - ISIG = 200mA - - - 22 - - - ISIG = 5.0mA VPP = +100V, VNN = -100V- - - 18 - - - ISIG = 200mA - - - 20 - - - ISIG = 5.0mA VPP = +160V, VNN = -40V- - - 16 - - - ISIG = 200mA ΔRONS Small signal switch ON-resistance matching - 20 - 5.0 20 - 20 % I SIG = 5.0mA, VPP = +100V, VNN = -100V RONL Large signal switch ON-resistance - - - 30 - - - Ω V SIG = VPP - 10V, ISIG = 1.0A ISOL Switch OFF-leakage per switch - 5.0 - 1.0 10 - 15 μA VSIG = VPP - 10V, VNN + 10V VOS DC offset switch OFF - 300 - 100 300 - 300 mV 100kΩ load DC offset switch ON - 500 - 100 500 - 500 IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches OFF INNQ Quiescent VNN supply current - - - -10 -50 - - IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches ON, I SW = 5.0mAINNQ Quiescent VNN supply current - - - -10 -50 - - ISW Switch output peak current - - - 2.0 1.3 - - A VSIG duty cycle < 0.1% fSW Output switching frequency - - - - 50 - - kHz Duty cycle = 50% IPP Average VPP supply current mA VPP= +40V, VNN = -160V All output switches are turning ON and OFF at 50kHz with no load PP= +100V, VNN = -100V VNN = -40V INN Average VNN supply current mA VPP = +40V, VNN = -160V All output switches are turning ON and OFF at 50kHz with no load PP= +100V, VNN = -100V VNN = -40V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 μA All logic inputs are static CIN Logic input capacitance - 10 - - 10 - 10 pF --- * See Test Circuits on page 5

Supertex inc. www.supertex.com Doc.# DSFP-HV2661 NR010913 Sym Parameter 0OC +25OC +70OC Unit Conditions Min Max Min Typ Max Min Max tSD Set up time before LE rises 25 - 25 - - 25 - ns --- tWLE Time width of LE 56 - - 56 - 56 - ns VDD = 3.0V 12 - - 12 - 12 - VDD = 5.0V tDO Clock delay time to data out 25 100 25 78 100 25 100 ns VDD = 3.0V 15 40 15 30 40 15 40 VDD = 5.0V tWCLR Time width of CLR 55 - 55 - - 55 - ns --- tSU Set up time data to clock 21 - 21 - - 21 - ns VDD = 3.0V tH Hold time data from clock ns VDD = 3.0V fCLK Clock frequency - 8 - - 8 - 8 MHz VDD = 3.0V - 20 - - 20 - 20 VDD = 5.0V tR, tF Clock rise and fall times - 50 - - 50 - 50 ns --- tON Turn ON time - 5.0 - - 5.0 - 5.0 μs VSIG = VPP - 10V, RLOAD = 10kΩtOFF Turn OFF time - 5.0 - - 5.0 - 5.0 dv/dt Maximum VSIG slew rate - 20 - - 20 - 20 V/ns VPP = +40V, VNN = -160V - 20 - - 20 - 20 VPP = +100V, VNN = -100V - 20 - - 20 - 20 VPP = +160V, VNN = -40V KO OFF isolation -30 - -30 -33 - -30 - dB f = 5.0MHz, 1.0kΩ//15pF load -58 - -58 -60 - -58 - f = 5.0MHz, 50Ω load K CR Switch crosstalk -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load IID Output switch isolation diode current - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle C SG(OFF) OFF capacitance SW to GND - 14 - 9.0 14 - 14 pF VSIG = 0V, f = 1.0MHz all SW OFFOFF capacitance Y to GND - 35 - 27 35 - 35 CSG(ON) ON capacitance SW to GND - 39 - 30 39 - 39 pF VSIG = 0V, f = 1.0MHz one SW ON, two SW OFFON capacitance Y to GND - 39 - 30 39 - 39 +VSPK Output voltage spike (per switch) - - - - 150 - - mV V PP = +40V, VNN = -160V RLOAD = 50Ω-VSPK - - - - 150 - - +VSPK - - - - 150 - - VPP = +100V, VNN = -100V RLOAD = 50Ω-VSPK - - - - 150 - - +VSPK - - - - 150 - - VPP = +160V, VNN = -40V RLOAD = 50Ω-VSPK - - - - 150 - - * See Test Circuits on page 5

Supertex inc. www.supertex.com Doc.# DSFP-HV2661 NR010913 Sym Parameter 0OC +25OC +70OC Unit Conditions Min Max Min Typ Max Min Max QC Charge injection (per switch) - - - 820 - - - pC V PP = +40V, VNN = -160V Test Circuits SW1SW0 SW1SW0 SW1SW0 SW1SW0 SW1SW0 SW1SW0 SW1SW0 SW1SW0 VPP -10V Switch OFF Leakage DC Offset ON/OFF TON/TOFF Test Circuit OFF Isolation Isolation Diode Current Charge Injection Output Voltage Spike SW VPP VPP VDD 5.0V VNN VNN GND VPP VPP VDD 5.0V VNN VNN GND VPP VPP VDD 5.0V VNN VNN GND VPP VPP VDD 5.0V VNN VNN GND VPP VPP VDD 5.0V VNN VNN GND VPP VPP VDD 5.0V VNN VNN GND VPP VPP VDD 5.0V VNN VNN GND VPP VPP VDD 5.0V VNN VNN GND Output Voltage Spike Y KO = 20Log VOUT VIN VIN = 10VP-P @5.0MHz RLOAD 10kΩ VOUT VOUT VOUT VOUT VOUT VOUT ΔVOUT NC NC NC NC NC NC VPP -10V ISOL VSIG IID VNN NC NC NC Q = 1000pF • ∆VOUT 50Ω 50Ω RL 1kΩ NC 1000pF +VSPK -VSPK +VSPK -VSPK RL 1kΩ 50Ω 50Ω VIN = 10VP-P @5.0MHz Crosstalk KCR = 20Log VOUT VIN 50Ω NC NC NC SW1 SW4SW3 SW0 VPP VPP VDD 5.0V VNN VNN GND VOUT SW2 NC SW2 NC SW2 NC SW2 NC SW2 NC SW2 NC SW5 NC NCSW2 NC SW2 NC SW2 100kΩ

Supertex inc. www.supertex.com Doc.# DSFP-HV2661 NR010913 Logic Timing Waveforms Truth Table DATA IN DIN LE CLOCK DATA OUT DOUT OFF VOUT (typ) ON CLR 50% 50% 50% 50% tWLE tSD 50% 50% tSU th tOFF 50% tDO tON tWCL DN + 1 DN DN - 1 50% 50% 90% 10% L - ... - - ... - L L OFF - ... - - ... X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF Notes: 1. The 24 switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. All 24 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch. 4. D OUT is high when data in the register 23 is high. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs.

Supertex inc. www.supertex.com Doc.# DSFP-HV2661 NR010913 Pin Function

1 VPP

3 GND

4 CLR

6 CLK

7 VDD

8 GND

9 DIN

10 DOUT

12 VNN

13 SW0

15 SW1

16 SW2

17 SW3

19 SW4

20 SW5

21 SW6

23 SW7

24 SW8

25 VPP

27 SW9

29 SW10

30 SW11

31 SW12

32 SW13

34 SW14

36 VNN

37 SW15

38 SW16

40 SW17

41 SW18

42 SW19

44 SW20

45 SW21

46 SW22

48 SW23

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com HV2661 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV2661 NR010913 48-Lead LQFP Package Outline (FG) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ Dimension (mm) 0.50 BSC 0.45 1.00 REF 0.25 BSC JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-48LQFPFG Version, D041309. Seating Plane Gauge Plane θL View B View B Seating Plane Top View Side View Note 1 (Index Area D1/4 x E1/4) A2A b D EE1 e Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.