HV2605FG-GM931

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Technical content

Features

► HVCMOS technology for high performance ► 16-channel high voltage analog switch ► 3.3V input logic level compatible ► 20MHz data shift clock frequency ► Very low quiescent power dissipation (-10µA) ► Low parasitic capacitance ► DC to 50MHz small signal frequency response ► -60dB typical off-isolation at 5.0MHz ► CMOS logic circuitry for low power ► Low harmonic distortion ► Cascadable serial data register with latches ► Flexible operating supply voltages

Applications

► Medical ultrasound imaging ► NDT metal flaw detection ► Piezoelectric transducer drivers ► Optical MEMS modules General Description The Supertex HV2605 is a low charge injection 16-channel high voltage analog switch integrated circuit (IC) intended for use in applications requiring high voltage switching controlled by low voltage control signals, such as medical ultrasound imaging and other piezoelectric transducer drivers. Input data are shifted into a 16-bit shift register that can then be retained in a 16-bit latch. To reduce any possible clock feed through noise, the latch enable bar should be left high until all bits are clocked in. Data are clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. The device is suitable for various combinations of high voltage supplies, e.g., V PP/VNN: +40V/-160V, +100V/-100V, and +160V/- 40V. Block Diagram Low Harmonic Distortion 16-Channel High Voltage Analog Switch Latches Level Shifters Output Switches SW2 16-Bit Shift Register VPPVNNCLRLEVDD GND DOUT CLK DIN SW14 SW15 SW1 SW0 D LE CLR D LE CLR D LE CLR D LE CLR D LE CLR

Supertex inc. www.supertex.com Doc.# DSFP-HV2605 B051512 YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Top Marking Bottom Marking YYWW HV2605FG LLLLLLLLL CCCCCCCC AAA Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Parameter Value VDD logic supply -0.5V to +7.0V VPP-VNN differential supply 220V VPP positive supply -0.5V to VNN+200V VNN negative supply +0.5V to -200V Logic input voltage -0.5V to VDD +0.3V Analog signal range VNN to VPP Peak analog signal current/channel 3.0A Storage temperature -65°C to 150°C Power dissipation: 48-Lead LQFP (FG) 1.0W Product Marking 48-Lead LQFP (FG) -G indicates package is RoHS compliant (‘Green’). Pin Configuration Sym Parameter Value VDD Logic power supply voltage 3.0 to 5.5V VPP Positive high voltage supply +40V to VNN +200V VNN Negative high voltage supply -40 to -160V VIH High level input voltage 0.9VDD to VDD VIL Low level input voltage 0 to 0.1VDD VSIG Analog signal voltage peak-to-peak VNN+10V to VPP-10V TA Operating free air temperature 0°C to 70°C Recommended Operating Conditions Notes: 1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2. VSIG must be within VNN and VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. Package may or may not include the following marks: Si or 48-Lead LQFP (FG) (top view)

Ordering Information

Part Number Package Option Packing HV2605FG-G 48-Lead LQFP 250/Tray HV2605FG-G M931 48-Lead LQFP 1000/Reel Typical Thermal Resistance Package θja 48-Lead LQFP 52OC/W

Supertex inc. www.supertex.com Doc.# DSFP-HV2605 B051512 Sym Parameter 0°C +25°C +70°C Units Conditions Min Max Min Typ Max Min Max RONS Small signal switch on-resistance - 30 - 26 38 - 48 Ω ISIG = 5.0mA VPP = +40V VNN = -160V- 25 - 22 27 - 32 ISIG = 200mA - 25 - 22 27 - 30 ISIG = 5.0mA VPP = +100V VNN = -100V- 18 - 18 24 - 27 ISIG = 200mA - 23 - 20 25 - 30 ISIG = 5.0mA VPP = +160V VNN = -40V- 22 - 16 25 - 27 ISIG = 200mA ∆RONS Small signal switch on-resistance matching - 20 - 5.0 20 - 20 % I SIG = 5.0mA, VPP = +100V, VNN = -100V RONL Large signal switch on-resistance - - - 15 - - - Ω V SIG=VPP -10V, ISIG = 1.0A ISOL Switch off leakage per switch* - 5.0 - 1.0 10 - 15 µA VSIG = VPP -10V and VNN +10V VOS DC offset switch off* - 300 - 100 300 - 300 mV 100KΩ loadDC offset switch on* - 500 - 100 500 - 500 mV IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches off INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches off IPPQ Quiescent VPP supply current - - - 10 50 - - µA All switches on, ISW = 5.0mA INNQ Quiescent VNN supply current - - - -10 -50 - - µA All switches on, ISW = 5.0mA fSW Output switching frequency - - - - 50 - - kHz Duty cycle = 50% IPP Average VPP supply current mA VPP = +40V VNN = -160V All output switches are turning on and off at 50KHz with no load. VPP = +100V VPP = +160V INN Average VNN supply current mA VPP = +40V VNN = -160V All output switches are turning on and off at 50KHz with no load. VPP = +100V VPP = +160V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 µA All logic inputs are static CIN Logic input capacitance - 10 - - 10 - 10 pF --- (over recommended operating conditions unless otherwise noted) * See Test Circuits on page 5

Supertex inc. www.supertex.com Doc.# DSFP-HV2605 B051512 (over recommended operating conditions, VDD= 5.0V, tR= tF ≤ 5ns, 50% duty cycle, CLOAD= 20pF unless otherwise noted) Sym Parameter 0°C +25°C +70°C Units ConditionsMin Max Min Typ Max Min Max tSD Set up time before LE rises 25 - 25 - - 25 - ns --- tWLE Time width of LE 56 - - 56 - 56 - ns VDD = 3.0V 12 - - 12 - 12 - VDD = 5.0V tDO Clock delay time to data out 50 100 50 78 100 50 100 ns VDD = 3.0V 15 40 15 30 40 15 40 VDD= 5.0V tWCLR Time width of CLR 55 - 55 - - 55 - ns --- tSU Set up time data to clock 21 - - 21 - 21 - ns VDD= 3.0V tH Hold time data from clock 2 - 2 - - 2 - ns VDD= 3.0 or 5.0V fCLK Clock frequency - 8 - - 8 - 8 MHz VDD= 3.0V - 20 - - 20 - 20 VDD= 5.0V tR,tF Clock rise and fall times - 50 - - 50 - 50 ns --- TON Turn on time* - 5.0 - - 5.0 - 5.0 µs VSIG = VPP -10V, RLOAD = 10KΩ TOFF Turn off time* - 5.0 - - 5.0 - 5.0 µs VSIG = VPP -10V, RLOAD = 10KΩ dv/dt Maximum VSIG slew rate - 20 - - 20 - 20 v/ns VPP = +40V, VNN = -160V - 20 - - 20 - 20 VPP = +100V, VNN = -100V - 20 - - 20 - 20 VPP = +160V, VNN = -40V KO Off isolation* dB f = 5.0MHz, 1KΩ//15pF load -58 - -58 - - -58 - f = 5.0MHz, 50Ω load KCR Switch crosstalk* -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load IID Output switch isolation diode current - 300 - - 300 300 mA 300ns pulse width, 2.0% duty cycle C SG(OFF) Off capacitance SW to GND - 15 - 10 15 - 15 pF VSIG = 0V, f = 1.0MHz CSG(ON) On capacitance SW to GND - 18 - 13 18 - 18 pF VSIG = 0V, f = 1.0MHz +VSPK Output voltage spike* - - - - 150 - - mV VPP = +40V, VNN = -160V, RLOAD = 50Ω-VSPK +VSPK RLOAD = 50Ω-VSPK +VSPK RLOAD = 50Ω-VSPK QC Charge injection* - - - 820 - - - pC VPP= +40V, VNN= -160V, VSIG= 0V - - - 600 - - - VPP= +100V, VNN= -100V, VSIG= 0V - - - 350 - - - VPP= +160V, VNN= -40V, VSIG= 0V * See Test Circuits on page 5

Supertex inc. www.supertex.com Doc.# DSFP-HV2605 B051512 Test Circuits DC Offset Switch ON/OFF VPP 5V VNN VPP VNN VDD GND VOUT TON/TOFF Test Circuit GND VPP -10V VOUT Output Switch Isolation Diode Current IID GND VNN VSIG Switch Crosstalk VIN = 10VP-P @5MHz NC GND 50Ω Output Voltage Spike GND VOUT 1kΩ +VSPK –VSPK OFF Isolation KO = 20Log VOUT VIN VIN = 10VP-P @5MHz GND VOUT 50Ω RLOAD VPP VNN VPP VNN VDD VPP VNN VPP VNN VDD VPP VNN VPP VNN VDD VPP VNN VPP VNN VDD VPP VNN VPP VNN VDD KCR = 20Log VOUT VIN VPP -10V Switch Off Leakage per Switch Q = 1000pF x ΔV OUT Charge Injection GND VPP VNN VPP VNN VDD VPP 5V VNN VPP VNN VDD Open ISOL GND VOUT ΔVOUT 1000pF RLOAD 100kΩ VSIG RLOAD 10kΩ RLOAD 50kΩ

Supertex inc. www.supertex.com Doc.# DSFP-HV2605 B051512 Logic Function Table Notes: 1. The 16 switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. All 16 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low the shift registers data flow through the latch. 4. DOUT is high when data in the shift register 15 is high. 5. Shift registers clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs. Logic Timing Waveforms DATA IN DIN LE CLOCK DATA OUT DOUT OFF ON CLR VOUT (typ) 50% 50% 50%50% tWLE tSD 50% 50% tSU th tOFF 50% tDO tON tWCL DN - 1DNDN + 1 50%50% 90% 10% L - ... - - ... - L L OFF - ... - - ... X X X X X X X H L HOLD PREVIOUS STATE X X X X X X X X H ALL SWITCHES OFF

Supertex inc. www.supertex.com Doc.# DSFP-HV2605 B051512 HV2605 Pin Description 48-Lead LQFP (FG) Pin # Function 1 NC 2 NC

3 SW4B

4 SW4A

5 SW3B

6 SW3A

7 SW2B

8 SW2A

9 SW1B

10 SW1A

11 SW0B

12 SW0A

Pin # Function

13 VNN

15 VPP

17 GND

18 VDD

19 DIN

20 CLK

22 CLR

23 DOUT

Pin # Function

25 SW15B

26 SW15A

27 SW14B

28 SW14A

29 SW13B

30 SW13A

31 SW12B

32 SW12A

33 SW11B

34 SW11A

Pin # Function

37 SW10B

38 SW10A

39 SW9B

40 SW9A

41 SW8B

42 SW8A

43 SW7B

44 SW7A

45 SW6B

46 SW6A

47 SW5B

48 SW5A

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) ©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888 www.supertex.com HV2605 (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV2605 B051512 48-Lead LQFP Package Outline (FG) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ Dimension (mm) 0.50 BSC 0.45 1.00 REF 0.25 BSC JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-48LQFPFG Version, D041309. Seating Plane Gauge Plane θ L View B View B Seating Plane Top View D E b e Side View A2 A Note 1 (Index Area D1/4 x E1/4) Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.